ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 38

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

RAM_ADDR[19:0]
RAM_BW_A#
RAM_BW_B#
RAM_BW_C#
RAM_BW_D#
RAM_BW_E#
RAM_BW_F#
RAM_BW_G#
RAM_BW_H#
RAM_RW#
Signal
Table 13 - External Memory Interface Package Ball Definition (continued)
I/O
O
O
O
O
O
O
O
O
O
O
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
U2
T3
U3
V2
W1
V3
W2
Y1
U4
R4
T2
T1
P5
R3
R2
P4
R1
P3
P2
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
38
P1
N4
N3
N2
M1
M2
M4
M3
M6
M5
Buffer memory address output.
Synchronous to rising edge of
SYSTEM_CLK.
Synchronous Byte Write Enable A (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[7:0].
Synchronous Byte Write Enable B (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[15:8].
Synchronous Byte Write Enable C (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[23:16].
Synchronous Byte Write Enable D (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[31:24].
Synchronous Byte Write Enable E (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[39:32].
Synchronous Byte Write Enable F (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[47:40].
Synchronous Byte Write Enable G (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[55:48].
Synchronous Byte Write Enable H (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[63:56].
Read/Write Enable output
Read = high
Write = low
Description
Data Sheet