ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet
ZL50408GDC
Related parts for ZL50408GDC
ZL50408GDC Summary of contents
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... U MII EEPROM Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. 1-Port 10/100/1000M Ethernet Switch ZL50408GDC broadcasting and flooding control • VLAN Support • Supports port-based VLAN and tagged-based VLAN (IEEE 802.1Q VLANs • ...
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Rate Control (both ingress and egress) • Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement) • Smooth out traffic to uplink port • Ingress Rate Control - ...
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Description The ZL50408 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100/1000 Mbps, and a CPU interface for managed, lightly managed and unmanaged ...
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BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tag-Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 101 13.3.8.4 RMAC_MIRROR0 – RMAC Mirror ...
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Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BGA and Ball Signal Descriptions 1.1 BGA Views (Top-View SCLK P_CS# P_RD# P_WE P_DAT # A1 B P_INT P_A0 P_A1 P_A2 P_DAT # A0 C RESET TSTO TSTO TSTO TSTO OUT# UT1 UT3 ...
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Ball Signal Descriptions All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive. Notes # = Active low signal Input = Input signal Input-ST = Input signal with Schmitt-Trigger ...
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Ball Signal Description Table (continued) Ball No(s) Symbol K15, R15, R12, R9, M[7:0]_TXEN R5, R2, L2, H2 J13, K13, J15, J16, M[7:0]_TXD[3:0] N16, P16, R16, T16, N13, P13, R13, T13, N10, P10, R10, T10, N6, P6, R6, T6, N3, P3, ...
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Ball Signal Description Table (continued) Ball No(s) Symbol A15 M9_MTXCLK A14 M9_TXCLK Test Interface C11, C10, D10, C9, TSTOUT[15:0] C8, D8, C7, D7, C6, C5, C4, D4, C3, D3, C2, D2 Test Facility C13 TDI C12 TRST# B13 TCK B14 ...
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Ball Signal Description Table (continued) Ball No(s) Symbol F1 M_MDC F2 M_MDIO R7 M_CLK A13 GREF_CLK Bootstrap Pins (1= pull up 0= pull down) D2 TSTOUT[0] C3, D3, C2 TSTOUT[3:1] C5, C4, D4 TSTOUT[6:4] C6 TSTOUT[7] D7 TSTOUT[8] C7 TSTOUT[9] ...
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Ball Signal Description Table (continued) Ball No(s) Symbol D8 TSTOUT[10] C8 TSTOUT[11] C9 TSTOUT[12] C11, C10, D10 TSTOUT[15:13] K15, R15, R12, R9, M[7:0]_TXEN R5, R2, L2, H2 A16, B15 M9_TXEN, M9_TXER 1. External pull-up/down resistors are required on all bootstrap ...
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Signal Mapping and Internal Pull Up/Down Configuration The ZL50408 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to ...
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The ZL50408 Gigabit Ethernet uplink port (port 9) supports 2 interface options: GMII & MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal ...
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The ZL50408 CPU access support 5 interface options 16-bit parallel, serial+MII (port 8), serial only, and unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each interface, and how they relate back to ...
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Bootstrap Options TSTOUT[15:0], M[7:0]_TXEN, M9_TXEN and M9_TXER pins serve as bootstrap pins during device power-up or reset. Please refer to “Typical Reset & Bootstrap Timing Diagram” on page 118 for more information on when the bootstrap pins are sampled. ...
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Block Functionality G GMAC Management Module 2.1 Internal Memory Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table database (MCT), and the Network Management (NM) Database statistics counters and MIB. ...
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CPU MAC Module (CMAC) The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external CPU device. It support either a Reverse MII interface, providing the necessary interface ...
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Search Engine The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2 multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority assignment, and trunking ...
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Lightly Managed Serial. Configuration registers access, Control frame and CPU transmit/receive packets are sent through a synchronous serial interface (SSI) bus. 5. Unmanaged Serial. The device can be configured by EEPROM using an I²C interface at bootup, or via ...
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Config Data Index Reg 1 Index Reg 0 Reg (Addr = 1) (Addr = 0) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access Figure 4 - Overview of the SSI Interface ZL50408 Processor Serial Out Serial ...
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Tclk Txd Txen Rxd Rxdv MII Interface Index Reg 1 (Addr = 1) 8/16-bit Data Bus 16-bit Address CPU frame Transmit CPU frame FIFO Receive FIFO 3.1 Register Configuration, Frame Transmission, and Frame Reception 3.1.1 Register Configuration The ZL50408 has ...
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CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address specified in index register and upper 8 bit of data is for the address + 1. In 8-bit mode, this special ...
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In summary, in 8/16-bit or serial only mode, receiving and transmitting frames to and from the CPU is a simple process that uses one direct access register only. In serial mode with MII interface, the CPU will be allowed to ...
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START SLAVE ADDRESS R/W Figure 6 - Data Transfer Format for I²C Interface 3.2.1 Start Condition Generated by the master (in our case, the ZL50408). The bus is considered to be busy after the Start condition is generated. The Start ...
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Each command consists of four parts. • START pulse • Register Address • Read or Write command • Data to be written or read back Write operation can be aborted in the middle by sending an ABORT pulse to the ...
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Data Forwarding Protocol 4.1 Unicast Data Frame Forwarding When a frame arrives assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. ...
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During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release ...
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When all the information is compiled, the switch response is generated, as stated earlier. The search engine also interacts with the CPU with regard to learning and aging. 5.3 Search, Learning, and Aging 5.3.1 MAC Search The search block performs ...
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Protocol Filtering Packet filtering can be performed based on protocol type field in the packets eight protocols can be programmed to filter or allow packet to pass through the switch. 5.6 Logical Port Filtering Similar to protocol ...
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Priority Classification Rule Figure 9 shows the ZL50408 priority classification rule. TOS Precedence over VLAN? Yes Use VLAN priority Use Default port settings 5.9 Port and Tag Based VLAN The ZL50408 supports two models for determining and controlling how ...
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Port Registers Register for Port #0 PVMAP00_0[7:0] to PVMAP00_1[1:0] Register for Port #1 PVMAP01_0[7:0] to PVMAP01_1[1:0] Register for Port #2 PVMAP02_0[7:0] to PVMAP02_1[1:0] … Register for Port #9 PVMAP09_0[7:0] to PVMAP09_1[1:0] For example, in the above table a 1 denotes ...
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IEEE 802.1Q Tagged Ethernet Frame Dest MAC Source MAC Tag Protocol ID (6 Bytes) (6 Bytes) IEEE 802.1Q-in-Q Tagged Ethernet Frame VLAN Dest MAC Source MAC Tag Protocol ID (6 Bytes) (6 Bytes) (0x88A8*) IEEE 802.1Q Tag TPID = 0x8100 ...
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A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are ...
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Port Control The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the ...
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However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. As Table 8 illustrates, the six traffic types may each have their own ...
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WRED Drop Threshold Management Support To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. High Drop Low Drop Px is the total ...
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Example : Suppose that the user wants to restrict Fast Ethernet port P’s average departure rate to 32 Mbps – 32% of line rate – when the average is taken over a period interval of ...
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The following registers define the size of each section of the Frame data Buffer: - PR100_N - Port Reservation for RMAC Ports - PR100_CPU - Port Reservation for CPU Port - PRG - Port Reservation for GMAC Port - SFCB ...
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The second method, by nature, lost the benefit of prioritization. See Programming Flow Control Registers application note, ZLAN-44, for more information. 7.7.1 Unicast ...
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Failover Backplane Feature The ZL50408 implements a hardware assisted link failure detection mechanism utilizing a Link Heart Beat (LHB) packet. The LHB packet format is defined as a 64-byte MAC control frame with a user defined opcode. The packet ...
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Multicast Packet Forwarding For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet based on the VLAN and hash key. Three functions are required in order to distribute multicast packets ...
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Device B, and loop back to itself, back to the cable and go back to Device A and the CPU. This way, the whole channel can be tested. CPU DEVICE A 10.0 GPSI (7WS) Interface ...
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If port 9 is not being used, GREF_CLK can be left unconnected. 11.1.4 JTAG Test Clock (TCK) speed requirements TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to “JTAG (IEEE 1149.1-2001)” ...
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Frame Send Fail B[2] 1-U Flow Control Frames Sent B[3] 2-I Non-Unicast Frames Sent B[4] 2-u Bytes Received (Good and Bad) (D) B[5] 3-d Frames Received (Good and Bad) (D) B[6] 4-d Total Bytes Received (D) B[7] 5-d Total Frames ...
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Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] ...
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FCSErrors Counts number of valid frames received with bad FCS. Frame size: No framing error No collisions 12.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions 12.2.1.5 FrameTooLongs ...
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Runts Counts number of frames received with size under 64 bytes, but greater than the length of a short event. Frame size: FCS error: Framing error: No collisions 12.2.1.8 Collisions Counts number of collision events. Frame size: 12.2.1.9 LateEvents ...
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IEEE 802.1 Bridge Management (RFC 1286) 12.3.1 Event Counters 12.3.1.1 InFrames Counts number of frames received by this port or segment. Note: A frame received by this port is only counted by this counter if and only if it ...
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CRCAlignErrors Counts number of frames received with FCS or alignment errors Frame size: No collisions: 12.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions 12.4.1.7 ...
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Jabbers Counts number of frames received with size exceeding maximum frame size and with bad FCS. Frame size: Framing error No collisions 12.4.1.10 Collisions Counts number of collision events detected. Only a best estimate since collisions can only be ...
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Register Definition 13.1 ZL50408 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 ...
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Register MULTICAST_HASHn-1 Multicast hash result n mask byte 1 3. CPU Port Configuration MAC0 CPU MAC Address byte 0 MAC1 CPU MAC Address byte 1 MAC2 CPU MAC Address byte 2 MAC3 CPU MAC Address byte 3 MAC4 CPU MAC ...
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Register 5. Global QOS Control QOSC QOS Control UCC Unicast Congestion Control MCC Multicast Congestion Control MCCTH Multicast Congestion Threshold RDRC0 WRED Drop Rate Control 0 RDRC1 WRED Drop Rate Control 1 RDRC2 WRED Drop Rate Control 2 SFCB Share ...
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Register WLPFD Well Known Logic Port Force Discard Enable USER_PORTn_LOW User Define Logical Port n Low USER_PORTn_HIGH User Define Logical Port n High USER_PORT1:0_ User Define Logic Port 0 PRIORITY and 1 Priority USER_PORT3:2_ User Define Logic ...
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Register USD One micro second divider DEVICE Device id and test SUM EEPROM Checksum Register LHBTimer Link heart beat time out timer LHBReg0 LHB control field value[7:0] LHBReg1 LHB control field value [15:8] fMACCReg0 Forced MAC control field value [7:0] ...
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Register MIRROR_SRC_MAC3 Mirror Source MAC Address 3 MIRROR_SRC_MAC4 Mirror Source MAC Address 4 MIRROR_SRC_MAC5 Mirror Source MAC Address 5 MIRROR_CONTROL Port Mirror Control Register RMAC_MIRROR0 RMAC Mirror 0 RMAC_MIRROR1 RMAC Mirror 1 8. Per Port QOS Control FCRn Flooding Control ...
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Register MASK0 MASK Timeout 0 MASK1 MASK Timeout 1 MASK2 MASK Timeout 2 MASK3 MASK Timeout 3 MASK4 MASK Timeout 4 BOOTSTRAP[2:0] BOOTSTRAP Read Back PRTFSMSTn Ethernet Port n Status Read Back PRTQOSSTn RMAC Port n QOS and Queue Status ...
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Register BM_RLSFF_INFO1 Bm_rlsfifo_info[15:8] BM_RLSFF_INFO2 Bm_rlsfifo_info[23:16] BM_RLSFF_INFO3 Bm_rlsfifo_info[31:24] BM_RLSFF_INFO4 Bm_rlsfifo_info[39:32] BM_RLSFF_INFO5 Fifo_cnt[2:0],Bm_rlsfifo_inf o[44:40] F. System Control GCR Global Control Register DCR Device Control Register DCR1 Device Control Register 1 DPST Device Port Status Register DTST Data read back register DA DA ...
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Directly Accessed Registers 13.2.1 INDEX_REG0 • Address for indirectly accessed register addresses (8/16 bits) • Address = 0 (write only) • In 16-bit or serial mode: Address bits [15:0] • In 8-bit mode: Address bits [7:0] 13.2.2 INDEX_REG1 (only ...
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When the CPU reads this register: Bit [0]: Control Frame receive buffer ready, CPU can write a new frame 1 – CPU can write a new control command 1 0 – CPU has to wait until this bit is ...
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Indirectly Accessed Registers 13.3.1 (Group 0 Address) MAC Ports Group 13.3.1.1 ECR1Pn: Port n Control Register I²C Address 000+n; CPU Address:0000+ port number) Accessed by CPU and I²C (R/W) Bit [ Flow Control Off 0 ...
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ECR2Pn: Port n Control Register I²C Address: 00A+n; CPU Address:0001+ port number) Accessed by CPU and I²C (R/W) Bit [0]: Filter untagged frame 0: Disable (Default) 1: All untagged frames from this port are discarded or follow ...
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Bit [7:6] Security Enable. The ZL50408 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress ...
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Bit [7] Link Heart Beat Transmit (RMAC ports only) 0: Disable (Default) 1: Enable 13.3.1.4 ECR4Pn: Port n Control Register I²C Address: 01E+n; CPU Address:0081+ port number) Accessed by CPU and I²C (R/W) Port 0 – 7: (RMAC ...
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Port 8: (CPU Port) Bit [1:0]: Reserved Bit [2]: Enable special write to 2 registers in a single write operation. 0: Disable (Default) 1: Enable Should be enabled only in serial mode and disabled in 8/16-bit mode. Bit [4:3]: Enable ...
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Bit [2]: Internal loopback. 0: Disable (Default) 1: Enable In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another ...
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Address) VLAN Group 13.3.2.1 AVTCL – VLAN Type Code Register Low I²C Address 028; CPU Address:h100 Accessed by CPU and I²C (R/W) Bit [7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0) 13.3.2.2 AVTCH ...
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In Tag based VLAN Mode Bit [3:0]: PVID [11:8] (Default is 0xF) Bit [4]: Untrusted Port. (Default is 1) This register is used to change the VLAN priority field of a packet to a predetermined priority. 1: VLAN priority field ...
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Bit [5:3]: Default Transmit priority. Used when Bit [7]=1 (Default 0) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 Transmit Priority Level 2 Transmit Priority Level 3 (Highest) Bit [6]: Default Discard priority. Used when Bit [7]=1 0 – ...
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Bit [3]: Flooding control in secure mode 0: Enable - Learning disabled port will not receive any flooding packets (Default) 1: Disable Bit [4]: Support MAC address 0 0: MAC address 0 is not learned. (Default) 1: MAC address 0 ...
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TRUNKn_HASH10 – Trunk group 0~7 hash result 1/0 destination port number CPU Address:h208+ trunk group) Accessed by CPU (R/W) Bit [3:0] Hash result 0 destination port number (Default 0) Bit [7:4] Hash result 1 destination port number ...
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Multicast Hash Registers Multicast Hash registers are used to distribute multicast traffic. 16 registers are used to form a 8-entry array; each entry has 10 bits, with each bit representing one port. Any port not belonging to a trunk group ...
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Address) CPU Port Configuration Group 5 MAC5 MAC4 MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC [5:0], the packet is forwarded to the CPU. 13.3.4.1 MAC0 – ...
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MAC5 – CPU MAC address byte 5 CPU Address:h305 Accessed by CPU (R/W) Bit [7:0]: Byte 5 of the CPU MAC address (Default 0) 13.3.4.7 INT_MASK0 – Interrupt Mask CPU Address:h306 Accessed by CPU (R/W) The CPU can dynamically ...
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INTP_MASKn – Interrupt Mask for MAC Ports 2~9 Registers INTP_MASK1 CPU Address:h311 (Ports 2,3) INTP_MASK2 CPU Address:h312 (Ports 4,5) INTP_MASK3 CPU Address:h313 (Ports 6,7) INTP_MASK4 CPU Address:h314 (Port CPU,GMAC) 13.3.4.10 RQS – Receive Queue Select CPU Address:h323 Accessed by ...
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MAC23 – Increment MAC port 2,3 address CPU Address:h326 Accessed by CPU (RW) Bit [2:0]: Bit [42:40] of Port 2 MAC address Bit [3]: Reserved Bit [6:4]: Bit [42:40] of Port 3 MAC address Bit [7]: Reserved 13.3.4.14 MAC45 ...
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CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command CPU Address:h330-336 Accessed by CPU, (R/W) 55 CQ6 CQ5 CQ4 CPU Queue insertion command Bit [9:0]: Destination Map (GMAC, CPU, port 7-0). Bit [13:10] Priority Bit [20:14] Number of granules for ...
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CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status CPU Address:h33A-33E Accessed by CPU, (R/W) CR4 CR3 CR2 CPU Queue insertion command Header pointer Bit [14:0]: Tail pointer Bit [30:15] Number of granules for the release Bit [38:32] 13.3.4.21 CPUGRNCTR – ...
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The default setting of AGETIME_LOW/HIGH provides 300 seconds aging time. Aging time is based on the following equation: {AGETIME_HIGH,AGETIME_LOW MAC entries in the memory X 800 µsec). Number of MAC entries = 4 K. 13.3.5.3 SE_OPMODE – ...
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Address) Buffer Control/QOS Group 13.3.6.1 QOSC – QOS Control I²C Address h04B; CPU Address:h500 2 Accessed by CPU and I C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 1 – Enable 0 – ...
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MCCTH – Multicast Threshold Control CPU Address: 512 Accessed by CPU (R/W) Threshold on the multicast granule count. Exceeding the threshold consider as Bit [7:0]: multicast resource low and the new multicast will be dropped flow ...
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SFCB – Share FCB Size I²C Address h074, CPU Address 518 Accessed by CPU and I²C (R/W) Bits [7:0]: Expressed in multiples of 16 granules. Buffer reservation for shared pool. 13.3.6.9 C1RS – Class 1 Reserve Size I²C Address ...
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AVPMM – VLAN Priority Map I²C Address h057, CPU Address:h531 Accessed by CPU and I²C (R/W) Map VLAN priority into eight level transmit priorities: Bit [0]: Priority when the VLAN tag priority field is 2 (Default 0) Bit [3:1]: ...
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TOSPML – TOS Priority Map I²C Address h059, CPU Address:h540 Accessed by CPU and I²C (R/W) Map TOS field in IP packet into eight level transmit priorities Bit [2:0]: Priority when the TOS field is 0 (Default 0) Bit ...
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Bit [3]: Frame drop priority when TOS field is 3 (Default 0) Bit [4]: Frame drop priority when TOS field is 4 (Default 0) Bit [5]: Frame drop priority when TOS field is 5 (Default 0) Bit [6]: Frame drop ...
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Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_Enable can individually turn on/off each Well Known Port if desired. Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select ...
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WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority I²C Address h0AB, CPU Address 563 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Bits[7:4]: Priority setting, transmission ...
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USER_PORT[7:0]_[LOW/HIGH] – User Define Logical Port 0~7 I²C Address h092+n(Low); CPU Address 570+2n(Low logical port number) I²C Address h09A+n(High); CPU Address 571+2n(High) Accessed by CPU and I²C (R/W) (Default 00) This register is duplicated eight times from ...
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USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority I²C Address h0A5, CPU Address 593 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for logic port 6 Bits[7:4]: Priority setting, transmission + dropping, for ...
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RLOWL – User Define Range Low Bit 7:0 I²C Address h0AE, CPU Address: 5A0 Accessed by CPU and I²C (R/W) Bits[7:0]: Lower 8 bit of the User Define Logical Port Low Range 13.3.6.36 RLOWH – User Define Range Low ...
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Address) MISC Group 13.3.7.1 MII_OP0 – MII Register Option 0 I²C Address 0BC, CPU Address:h600 Accessed by CPU and I²C (R/W) Bit [4:0]: Vendor specified link status register address (null value means don’t use it) (Default 00). ...
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Bit [4]: Disable IP Multicast Suppor t 0 – Enable IP Multicast Support (Must also set PVMODE[6]=1) 1 – Disable IP Multicast Support (Default) When enable, IGMP packets are identified by search engine and are passed to the CPU for ...
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MIIC2 – MII Command Register 2 CPU Address:h605 Accessed by CPU (R/W) Bit [4:0] REG_AD – Register PHY Address Bit [6:5] OP – Operation code “10” for read command and “01” for write command Bit [7] Reserved Note : ...
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USD – One Micro Second Divider CPU Address:h609 Accessed by CPU (R/W) Bits[5:0]: Divider to get one micro second from M_CLK (only used when not in standard RMII mode MII or GPSI system, a 50MHz M_CLK may ...
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LHBTimer – Link Heart Beat Timeout Timer CPU Address:h610 Accessed by CPU (R/W) In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half this period. ...
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Address) Port Mirroring Group 13.3.8.1 MIRROR CONTROL – Port Mirror Control Register CPU Address 70C Accessed by CPU (R/W) (Default 00) Bit [3:0]: Destination port to be mirrored to. Bit [4] Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0] ...
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RMAC_MIRROR1 – RMAC Mirror 1 CPU Address 711 Accessed by CPU (R/W) Bit [2:0]: Source port to be mirrored Bit [3]: Mirror path 0: Receive 1: Transmit Bit [6:4]: Destination port for mirrored traffic Bit [7]: Mirror enable 13.3.9 ...
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BMRCn - Port 0~9 Broadcast/Multicast Rate Control I²C Address h05E+n, CPU Address:h820 port number) Accessed by CPU and I²C (R/W) This broadcast and multicast rate defines for Port n, the number of packets allowed to be forwarded ...
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PTHG – Port GMAC Threshold I²C Address h0CA, CPU Address 869 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow ...
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QOSC28 - QOSC31 - Classes WFQ Credit For GMAC Accessed by CPU (R/W) W0 – QOSC28[5:0] – CREDIT_C00 (CPU Address 89C) W1 – QOSC29[5:0] – CREDIT_C01 (CPU Address 89D) W2 – QOSC30[5:0] – CREDIT_C02 (CPU Address 89E) W3 – ...
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TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8] CPU Address E02, E03 Accessed by CPU (RO) 13.3.10.4 MASK0-MASK4 – Timeout Reset Mask CPU Address E10-E14 Accessed by CPU (R/W) Disable timeout reset on selected state machine status. See Programming Timeout ...
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PTCTL NOT idle for 5 sec Bit [4]: Reserved Bit [5]: LHB frame detected Bit [6] LHB receiving timeout Bit [7]: 13.3.10.7 PRTQOSST0-PRTQOSST7 CPU Address EA0+n Accessed by CPU (RO) Source port reservation low Bit [0]: No source port buffer ...
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Bit [10]: priority 0 MC queue full Bit [11]: priority 1 MC queue full Bit [12]: priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bit [15:14]: Reserved 13.3.10.9 PRTQOSST9A, PRTQOSST9B (GMAC port) CPU Address EAA – ...
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CLASSQOSST CPU Address EAC Accessed by CPU (RO) Bit [0]: No share buffer Bit [1]: No class 1 buffer Bit [2]: No class 2 buffer Bit [3]: No class 3 buffer Bit [7:4]: Reserved 13.3.10.11 PRTINTCTR CPU Address EAD ...
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QCTRL CPU Address EBA Accessed by CPU (R/W) Stop QM FSM at idle Bit [0]: Stop MCQ FSM at idle Bit [1]: Stop new granule grant to any source Bit [2]: Stop release granule from any source Bit [3]: ...
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BUFF_RST CPU Address EC0 Accessed by CPU (R/W) Bit [3:0] Assign a value that the pool to be reset 0: port 0 pool 1: port 1 pool 2: port 2 pool 3: port 3 pool 4: port 4 pool ...
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FCB_TAIL_PTR0, FCB_TAIL_PTR1 CPU address EC3 Accessed by CPU (R/W) Bit [7:0] Fcb_tail_ptr[7:0]. The tail pointer of free granule link that CPU assigns. CPU address EC4 Accessed by CPU (R/W) Bit [6:0] Fcb_tail_ptr[14:8]. The tail pointer of free granule link ...
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BM_RSLFF_INFO[5:0] CPU address EC8 Accessed by CPU (RO) Bit [7:0] Rls_head_ptr[7:0]. CPU address EC9 Accessed by CPU (RO) Bit [6:0] Rls_head_ptr[14:8]. Bit [7] Rls_tail_ptr[0] CPU address ECA Accessed by CPU (RO) Bit [7:0] Rls_tail_ptr[8:1] CPU address ECB Accessed by ...
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F Address) CPU Access Group 13.3.11.1 GCR - Global Control Register CPU Address: hF00 Accessed by CPU (R/W) Bit [0]: Store configuration (Default = 0) Write ‘1’ followed by ‘0’ to store configuration into external EEPROM Bit [1]: ...
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DCR1 - Device Status Register 1 CPU Address: hF02 Accessed by CPU (RO) Bit [6:0] Reserved Bit [7] Chip initialization completed 13.3.11.4 DPST – Device Port Status Register CPU Address:hF03 Accessed by CPU (R/W) Bit [4:0]: Read back index ...
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DA – DA Register CPU Address: hFFF Accessed by CPU (RO) Always return 8’ Indicate the CPU interface or serial port connection is good. Bit [7:0] Always return DA 14.0 Characteristics and Timing 14.1 Absolute Maximum Ratings ...
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Recommended Operating Conditions Symbol Parameter Description f Frequency of Operation (SCLK) osc I V Supply Current – @ 100 MHz (full line rate Supply Current – @ 100 MHz (full line rate ...
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AC Characteristics and Timing 14.4.1 Typical Reset & Bootstrap Timing Diagram RESIN# RESETOUT# R1 Bootstrap Pins Outputs Figure 13 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# ...
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Typical CPU Timing Diagram for a CPU Write Cycle P_A[2:0] P_CS# T P_WE# P_DATA (to device) Set up time Figure 14 - Typical CPU Timing Diagram for a CPU Write Cycle Description Write Cycle Symbol Write Set up Time ...
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Typical CPU Timing Diagram for a CPU Read Cycle P_A[2:0] P_CS P_RD# P_DATA (to CPU) Valid time Figure 15 - Typical CPU Timing Diagram for a CPU Read Cycle Description Read Cycle Symbol Read Set up Time ...
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Reduced Media Independent Interface Figure Characteristics – Reduced media independent Interface (TX) Figure Characteristics – Reduced Media Independent Interface (RX) Symbol Parameter M2 M[7:0]_RXD[1:0] Input Setup Time M3 M[7:0]_RXD[1:0] Input Hold Time M4 ...
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Media Independent Interface Figure Characteristics – Media independent Interface (TX) Figure Characteristics – Media Independent Interface (RX) Symbol Parameter MM2 M[9,7:0]_RXD[3:0] Input Setup Time MM2 M[8]_RXD[3:0] Input Setup Time MM3 Mn_RXD[3:0] Input Hold ...
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General Purpose Serial Interface (7-wire) Figure Characteristics – General Purpose Serial Interface (TX) Figure Characteristics – General Purpose Serial Interface (RX) Symbol Parameter SM2 M[7:0]_RXD Input Setup Time SM3 M[7:0]_RXD Input Hold Time ...
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Gigabit Media Independent Interface Figure Characteristics- Gigabit Media Independent Interface (TX) Figure Characteristics – Gigabit Media Independent Interface (RX) ZL50408 M9_TXCLK G12-max G12-min M9_TXD [7:0] G13-max G13-min M9_TXEN G14-max G14-min M9_TXER M9_RXCLK M9_RXCLK ...
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Symbol Parameter G1 M9_RXD[7:0] Input Setup Times G2 M9_RXD[7:0] Input Hold Times G3 M9_RXDV Input Setup Times G4 M9_RXDV Input Hold Times G5 M9_RXER Input Setup Times G6 M9_RXER Input Hold Times G7 M9_CRS Input Setup Times G8 M9_CRS Input ...
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MDIO Input Setup and Hold Timing Figure 24 - MDIO Input Setup and Hold Timing Symbol Parameter D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50408 MDC D1 D2 MDIO MDC D3-max ...
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I²C Input Setup Timing Symbol Parameter S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50408 SCL S2 S1 ...
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Serial Interface Setup Timing STROBE Datain STROBE Dataout Figure 29 - Serial Interface Output Delay Timing Symbol Parameter D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ...
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JTAG (IEEE 1149.1-2001) TCK TMS, TDI J3-max TDO J3-min Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK ...
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Document Errata 15.1 July 2003 • Initial Release 15.2 November 2003 • Clarified IP Multicast support groups wasn’t mentioned in the data sheets • Updated Ball Signal Description Table : • clarified the ...
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TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN DATE 14Nov02 APPRD. BOTTOM VIEW b Previous package codes MIN MAX Dimension 1. 0.30 0.50 A2 0.53 REF D 16.90 17.10 16.90 17.10 ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...