ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 14

• Manufacturer Part Number: ZL50408GDC
• Description: Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Ball Signal Description Table (continued)
A15
A14
Test Interface
C11, C10, D10, C9,
C8, D8, C7, D7, C6,
C5, C4, D4, C3, D3,
C2, D2
Test Facility
C13
C12
B13
B14
D11
D6
System Clock, Power, and Ground Pins
A1
D9, H4, H13, N7,
D5, D12, E4, E13, M4,
M13, N5,
G7-10, H7-10, J7-10,
K7-10
Misc.
D1
C1
Ball No(s)
M9_MTXCLK
M9_TXCLK
TSTOUT[15:0]
TDI
TRST#
TCK
TMS
TDO
SCAN_EN
SCLK
V
V
V
RESIN#
RESETOUT#
DD
CC
SS
Symbol
Input
w/ pull up
Output
Output
Input
w/pull up
Input
w/pull up
Input
w/pull up
Input
w/pull up
Output
Input
Must be externally
pulled-down
Input
Power
Power
Power Ground
Input
Output
Zarlink Semiconductor Inc.
ZL50408
I/O
14
Gigabit Transmit Clock
[15:4] Reserved
JTAG - Test Data Out
+1.8 Volt DC Supply
+3.3 Volt DC Supply
Reset PHY
Transmit Clock
[3] EEPROM checksum is good
[2] Initialization Completed
[1] Memory Self Test in progress
[0] Initialization started
These pins also serve as bootstrap pins.
JTAG - Test Data In
JTAG - Test Reset
JTAG - Test Clock
JTAG - Test Mode State
Scan Enable. Manufacturing test option.
Should be externally pulled-down for proper
operation.
System Clock. Based on system requirement,
SCLK needs to operate at difference
frequency.
SCLK requires 40/60% duty cycle clock.
Ground
Reset Input
Description
Data Sheet