ZL50408GDC ZARLINK [Zarlink Semiconductor Inc], ZL50408GDC Datasheet - Page 120

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ZL50408GDC

Manufacturer Part Number
ZL50408GDC
Description
Managed 8-Port 10/100M 1-Port 10/100/1000M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
14.4.3
Read Set up Time
Read Active Time
Read Hold Time
Read Recovery time
Data Valid time
Data Invalid time
P_A[2:0]
P_CS#
P_RD#
P_DATA
(to CPU)
Read Cycle
Typical CPU Timing Diagram for a CPU Read Cycle
Description
Figure 15 - Typical CPU Timing Diagram for a CPU Read Cycle
Valid time
Symbol
Table 16 - AC Characteristics - CPU Read Cycle
T
T
T
T
T
T
T
RS
RS
RA
RH
RR
Dv
DI
ADDR0
T
DV
2 SCLKs
at least
(SCLK=100 Mhz)
T
Min.
10
20
30
RA
Zarlink Semiconductor Inc.
2
DATA0
ZL50408
T
T
RH
DI
Max.
120
12
10
Invalid time
Recovery Time
(SCLK=50 Mhz)
T
Min.
RR
10
40
60
2
T
RS
Max.
12
10
ADDR1
T
DV
2 SCLKs
at least
At least 2 SCLK
At least 3 SCLK
T
RA
Refer to Figure 15
DATA1
T
T
RH
DI
Data Sheet

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