ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 107

• Manufacturer Part Number: ZL50418GKC
• Description: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.12
14.12.1
CPU Address: hF00
Accessed by CPU and serial interface. (R/W)
14.12.2
CPU Address: hF01
Accessed by CPU and serial interface. (RO)
Group F Address) CPU Access Group
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [5:4]:
GCR-Global Control Register
DCR-Device Status and Signature Register
7
7
Revision
6
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Initialization Done (Default = 0).
This bit is meaningless in unmanaged mode. In managed mode, CPU write
this bit with ‘1’ to indicate initialization is completed and ready to forward
packets.
1 = Initialization is done.
0 = Initialization is not complete.
1: Busy writing configuration to I
0: Not busy (not writing configuration to I
1: Busy reading configuration from I
0: Not busy (not reading configuration from I
1: BIST in progress
0: BIST not running
1: RAM Error
0: RAM OK
Device Signature
11: ZL50418 device
5
5
Signature
4
Init
4
3
Reset
Zarlink Semiconductor Inc.
3
RE
ZL50418
107
2
Bist
2
C
2
BinP
2
C
1
SR
2
C)
2
C)
0
SC
1
BR
0
BW
Data Sheet