ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 149
![no-image](/images/no-image-200.jpg)
ZL50418GKC
Manufacturer Part Number
ZL50418GKC
Description
Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50418GKC.pdf
(163 pages)
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15.5.6
P_ADDR
P_CS#
P_RD#
DATA to CPU
Typical CPU Timing Diagram for a CPU Read Cycle
Read Cycle
Read Set up Time
Read Active Time
Read Hold Time
Read Recovery time
Data Valid time
Data Invalid time
Figure 20 - Typical CPU Timing Diagram for a CPU Read Cycle
Description
Valid time
T
RS
T
T
T
T
T
T
RS
RA
RH
RR
Dv
DI
Symbol
T
DV
2 SCLKs
at least
Table 18 - Read Cycle
Zarlink Semiconductor Inc.
T
ADDR0
RA
DATA 0
ZL50418
(SCLK=100 Mhz)
149
T
T
Min.
RH
DI
10
20
30
2
Recovery Time
at least 3 SCLKs
Invalid time
T
Max.
RR
10
6
2ns
T
RS
At least 2 SCLK
At least 3 SCLK
Refer to Figure 20
ADDR1
T
DV
2 SCLKs
at least
T
RA
DATA 1
T
RH
T
DI
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