ZL50418GKC ZARLINK [Zarlink Semiconductor Inc], ZL50418GKC Datasheet - Page 60

• Manufacturer Part Number: ZL50418GKC
• Description: Managed 16-Port 10/100 M + 2-Port 1 G Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.2
14.2.1
•
•
14.2.2
•
•
14.2.3
•
•
14.2.4
•
•
•
14.2.5
•
•
•
Address bits [7:0] for indirectly accessed register addresses
Address = 0 (write only)
Address bits [15:8] for indirectly accessed register addresses
Address = 1 (write only)
Data of indirectly accessed registers. (8 bits)
Address = 2 (read/write)
CPU transmit/receive switch frames. (8/16 bits)
Address = 3 (read/write)
Format:
CPU interface commands (write) and status
Address = 4 (read/write)
When the CPU writes to this register
- Send frame from CPU: In sequence)
- CPU Received frame: In sequence)
-
-
-
-
Directly Accessed Registers
Frame Data (size should be in multiple of 8-byte)
8-byte of Frame status (Frame size, Destination port #, Frame O.K. status)
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data
INDEX_REG0
INDEX_REG1 (only needed for 8-bit mode)
DATA_FRAME_REG
CONTROL_FRAME_REG
COMMAND&STATUS Register
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
•
•
•
•
•
Set Control Frame Receive buffer ready, after CPU writes a complete frame
into the buffer. This bit is self-cleared.
Set Control Frame Transmit buffer1 ready, after CPU reads out a complete
frame from the buffer. This bit is self-cleared.
Set Control Frame Transmit buffer2 ready, after CPU reads out a complete
frame from the buffer. This bit is self-cleared.
Set this bit to indicate CPU received a whole frame (transmit FIFO frame
receive done), and flushed the rest of frame fragment, If occurs. This bit will
be self-cleared.
Set this bit to indicate that the following Write to the Receive FIFO is the last
one (EOF). This bit will be self-cleared.
Zarlink Semiconductor Inc.
ZL50418
60
Data Sheet