S71WS512NB0BAEZZ0 SPANSION [SPANSION], S71WS512NB0BAEZZ0 Datasheet
S71WS512NB0BAEZZ0
Related parts for S71WS512NB0BAEZZ0
S71WS512NB0BAEZZ0 Summary of contents
Page 1
S71WS512NE0BFWZZ Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory and Pseudo-Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Operating Voltage Range of 1.65 to 1.95 V High Performance — Speed: 54MHz Packages — ...
Page 2
Product Selector Guide Device-Model # SRAM/pSRAM Density S71WS512NE0BFWZZ 256Mb SRAM/pSRAM Type Supplier pSRAM - x16 COSMORAM 1 S71WS512NE0BFWZZ Flash Access RAM ...
Page 3
TABLE OF CONTENTS S71WS512NE0BFWZZ Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . ...
Page 4
Chip Erase Command Sequence ................................................................... 58 Sector Erase Command Sequence .................................................................59 Erase Suspend/Erase Resume Commands .................................................. 60 Figure 4. Erase Operation.................................................... 61 Program Suspend/Program Resume Commands ...................................... 61 Lock Register Command Set Definitions ................................................... 62 Password Protection Command Set Definitions ...
Page 5
CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted 110 ASYNCHRONOUS READ OPERATION ...
Page 6
Block Diagrams MCP Block Diagram of S71WS512NE0BFWZZ AVD# CLK WE# OE# RESET# CE#f1 ACC WP# CE#f2 LB# UB# CE#1pS-1 CE2pS-1 CE#1pS-2 CE2pS ...
Page 7
Connection Diagrams Connection Diagram of S71WS512NE0BFWZZ AVD CE#f1 K2 CE#1pS_1 L2 RFU M2 ...
Page 8
Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (FBGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Pin ...
Page 9
Logic Symbol NOR Flash and pSRAM and DATA STORAGE densities Gigabits The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package ...
Page 10
Device Bus Operation Operation (Asynchronous) - Flash CE#f1 CE#f2 CE#1pS_1 CE2pS_1 CE#1pS_2 CE2pS_2 OE Read - Address Latched Read - Address Steady State Write H ...
Page 11
The order number (Valid Combination) is formed by the following 512 Valid Combinations list configurations planned to be supported in volume for this device. Consult ...
Page 12
Valid Combinations Order Number Package Marking S71WS512NE0BFWZZ 71WS512NE0BFWZZ Pin Capacitance Symbol Parameter C Input Capacitance IN1 C Output Capacitance IN2 C Control Capacitance out ...
Page 13
Physical Dimensions TBD XXX June 28, 2004 S71WS512NE0BFWZZ_00_A1 ...
Page 14
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S29WS256N 256 Megabit ( 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Distinctive Characteristics Architectural Advantages Single 1.8 volt read, program and erase (1.65 to 1.95 volt) Manufactured ...
Page 15
Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Program Suspend/Resume — Suspends a programming ...
Page 16
General Description The WSxxxN is a 256 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 16 Mwords of 16 bits. This device uses a sin- gle V of 1. read, program, and ...
Page 17
wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and then ...
Page 18
The sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V ically ...
Page 19
Product Selector Guide Part Number V Option IO Speed Option (Burst Frequency) (Note 1) Max Synchronous Latency Max Synchronous Burst Access Time Max Asynchronous Access Time t Max CE# ...
Page 20
Block Diagram of Simultaneous Operation Circuit Amax–A0 WP# Amax–A0 ACC STATE RESET# CONTROL WE# & CE# COMMAND AVD# REGISTER RDY DQ15–DQ0 Amax–A0 Amax–A0 Amax–A0 Notes: Amax=A23 for the WS256N. 20 S29WSxxxN MirrorBit™ Flash Family ...
Page 21
Input/Output Descriptions A23-A0 DQ15-DQ0 CE# OE# WE SSIO NC RDY CLK AVD# RESET# WP# ACC June 28, 2004 S71WS512NE0BFWZZ_00_A1 S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products ...
Page 22
Logic Symbol Max*+1 * max=23 for the WS256N. 22 S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004 ...
Page 23
Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory ...
Page 24
Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst read and linear burst read of a preset length. When the device first powers up enabled for asynchro- nous read operation. Prior to entering ...
Page 25
8-, 16-, and 32-Word Linear Burst with Wrap Around The remaining three burst read modes are of the linear wrap around design, in which a fixed number of words are read from consecutive ...
Page 26
Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while program- ming or erasing in another bank of memory. An erase operation may also be suspended to read from or program ...
Page 27
pass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing V embedded program or erase operation, returns the device to normal operation. Note that sectors must be ...
Page 28
Any other address/data write combinations will abort the Write Buffer Program- ming operation. The device will then “go busy.” The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates ...
Page 29
tion. Note that if a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from ...
Page 30
Password Mode Lock Bit In order to select the Password Sector Protection scheme, the customer must first program ...
Page 31
Unlocked—The sector is unprotected and can be changed by a simple com- mand In order to achieve these states, three types of “bits” namely Persistent Protec- tion Bit (PPB), Dynamic Protecton Bit (DYB), ...
Page 32
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset, the DYBs are set or cleared depending upon the ordering op- tion chosen. If the option to clear the DYBs after ...
Page 33
tected sector enables status polling and returns to read mode without having modified the contents of the protected sector. The programming of the DYB, PPB, and PPB Lock for a given sector can ...
Page 34
Lock Register The Lock Register consists of 4 bits. The Customer SecSi Sector Protection Bit is DQ0, Persistent Protection Mode Lock Bit is DQ1, Password Protection Mode Lock Bit is DQ2, and Persistent Sector Protection OTP Bit is DQ3. Each ...
Page 35
Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one ...
Page 36
RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase ...
Page 37
random, secure ESN only within the Factor SecSi Sector Customer code within the Customer SecSi Sector through the Spansion gramming service Both a random, secure ESN and customer code through the Spansion ...
Page 38
Table 11 within the bank, will return non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command ...
Page 39
Addresses Data 27h 0019h (WS256N) 28h 0001h 29h 0000h 2Ah 0005h 2Bh 0000h 2Ch 0003h 2Dh 0003h 2Eh 0000h 2Fh 0080h 30h 0000h 31h 00FDh (WS256N) 32h 0000h 33h 0000h 34h 0002h 35h ...
Page 40
Table 11. Primary Vendor-Specific Extended Query (Continued) Addresses Data 4Bh 0001h 4Ch 0000h 4Dh 0085h 4Eh 0095h 4Fh 0001h 50h 0001h 51h 0001h 52h 0007h 53h 0014h 54h 0014h 55h 0005h 56h 0005h 57h 0010h 58h 0013h (WS256N) 59h 0010h ...
Page 41
Table 12. Sector Address / Memory Address Map for the WS256N Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 Bank 0 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 ...
Page 42
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 Bank 2 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 ...
Page 43
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 Bank 4 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 ...
Page 44
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 Bank 6 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 ...
Page 45
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 Bank 8 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 ...
Page 46
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 Bank 10 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 ...
Page 47
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 Bank 12 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 ...
Page 48
Table 12. Sector Address / Memory Address Map for the WS256N (Continued) Bank Sector SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 Bank 14 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 ...
Page 49
Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The defines the valid register command sequences. Writing incorrect address and data values or writing them ...
Page 50
The configuration register can not be changed during device operations (program, erase, or sector lock). Read Configuration Register Command Sequence The configuration register can be read with a four-cycle command sequence. The first two cycles are standard unlock ...
Page 51
Table 13. Programmable Wait State Settings CR13 Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default ...
Page 52
Burst Sequence Only sequential burst is allowed in the device. CR7 defaults to a ‘1’ and must al- ways be set to a ‘1’. Burst Length Configuration The device supports four different read modes: continuous mode, and 8, 16, and ...
Page 53
case, the RDY pin will always indicate that the device is ready to handle a new transaction when low. Configuration Register Table 16 shows the address bits that determine the configuration register settings ...
Page 54
The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This re- sets the bank to which the system was writing to the read mode. If the ...
Page 55
Description Device ID, Word 2 Device ID, Word 3 Indicator Bits The system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank was previously ...
Page 56
When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write ...
Page 57
Figure 2. Write Buffer Programming Operation Unlock Bypass Command Sequence The unlock bypass feature allows faster programming than the standard program command sequence. The unlock bypass command sequence is initiated by first writing ...
Page 58
The host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. The "Command ...
Page 59
erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings ...
Page 60
DQ7 or DQ6/DQ2 in the erasing bank. Refer to formation on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset im- ...
Page 61
Notes: 1. See the "Command Definition 2. See the section on DQ3 for information on the sector erase timer. Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt an ...
Page 62
Program Suspend command can be written after the device has resumed programming. Lock Register Command Set Definitions The Lock Register Command Set permits the user to program the SecSi Sector Protection Bit, Persistent Protection Mode Lock Bit, or Password Protection ...
Page 63
Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” ...
Page 64
PPB status for that sector. Writes within that bank, will set the PPB for that sector. Reads from other banks are allowed, writes are not al- lowed. All Reads must be performed using the Asynchronous mode. ...
Page 65
Volatile Sector Protection Command Set The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of ...
Page 66
Command Definition Summary Command Sequence (Note 1) Addr Asynchronous Read (Note 7) 1 Reset (Note 8) 1 XXX Manufacturer ID 4 555 Device ID (Note 10) 6 555 Indicator Bits 4 555 Program 4 555 Write to Buffer (Note 18) ...
Page 67
(Continued) Command Sequence (Note 1) Addr Password Protection Command Set Entry (Note 3 555 23) Password Program* 2 Password Read** 4 Password Unlock*** 7 Password Protection Command Set Exit (Note 2 26) Non-Volatile ...
Page 68
Legend Don’t care RA = Address of the memory location to be read Data read from location RA during read operation Address of the memory location to be programmed. Addresses latch on the rising ...
Page 69
Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. sections describe the function of these bits. DQ7 ...
Page 70
RDY: Ready The RDY is a dedicated output, controlled by CE#, that indicates the number of clock cycles in the system should write before expecting valid data. When the de- vice is configured in the Synchronous mode and RDY is ...
Page 71
array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 ...
Page 72
DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II ...
Page 73
system tasks. In this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation. Refer to for more details. DQ5: Exceeded ...
Page 74
Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Program Suspended Program Sector Suspend Mode Reading within Non-Program (Note 3) Suspended Sector Suspended Sector Erase-Suspend- Erase Read Suspend Mode Suspended Sector Erase-Suspend-Program BUSY State Write to Buffer Exceeded ...
Page 75
Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 76
DC Characteristics CMOS Compatible Parameter Description I Input Load Current LI I Output Leakage Current (Note Active burst Read Current CCB Non-active Output IO1 IO V Active Asynchronous Read Current CC I CC1 ...
Page 77
Test Conditions Test Condition Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Switching Waveforms WAVEFORM ...
Page 78
V Power-up CC Parameter Description t V Setup Time VCS Setup Time VIOS IO Note > 100mV and ramp rate <1V / 100µs, a Hardware Reset will ...
Page 79
Characteristics—Synchronous CLK Characterization Parameter Description f CLK Frequency CLK t CLK Period CLK t CLK High Time CH t CLK Low Time CL t CLK Rise Time CR t CLK Fall Time ...
Page 80
Synchronous/Burst Read @ V Parameter JEDEC Standard t IACC t Burst Access Time Valid Clock to Output Delay BACC t Address Setup Time to CLK ACS t Address Hold Time from CLK ACH t Data Hold Time from Next Clock ...
Page 81
Timing Diagrams t CES CE# 1 CLK t AVC AVD# t AVD t ACS Addresses Aa t ACH Data (n) OE# Hi-Z RDY ( Data ( Hi-Z RDY (n ...
Page 82
CAS CE# 1 CLK t AVC AVD# t AVD t AAS Addresses Aa t AAH Data OE Hi-Z RDY Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait ...
Page 83
cycles for initial access shown. t CES CE CLK t AVC AVD# t AVD t ACS AC Addresses t ACH Data OE Hi-Z RDY Notes: 1. ...
Page 84
AC Characteristics—Asynchronous Asynchronous Mode Read @ Parameter JEDEC Standard Asynchronous Access Time ACC t AVDP t Address Setup Time to Rising Edge of AVD# AAVDS t Address Hold Time from Rising Edge of AVD# AAVDH t OE ...
Page 85
CE# OE# WE# Data Addresses AVD# Note Read Address Read Data. Hardware Reset (RESET#) Parameter JEDEC Std t RP Reset High Time Before Read (During Embedded Algorithms ...
Page 86
Erase/Program Operations @ V Parameter JEDEC Standard t t AVAV Address Setup Time (Notes 2, 3) AVWL Address Hold Time (Notes 2, 3) WLAX AH t AVDP t t DVWH WHDX ...
Page 87
CLK AVD AVD Addresses 555h Data t CA CE# OE# WE Notes Program Address, PD ...
Page 88
CLK AVSC AVD Addresses 555h Data t CA CE# OE# WE Notes Program Address Program Data Valid Address for reading status bits. 2. “In progress” and ...
Page 89
AVD# CE OE# t OEH WE# Addresses Data Notes: 1. Status reads in figure are shown as asynchronous Valid Address. Two read cycles are required to determine status. ...
Page 90
CE# CLK AVD# Addresses V A OE# Data RDY Notes: 1. The timings are similar to synchronous read timings Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the ...
Page 91
C124 CLK 7C Address (hex) (stays high) AVD# RDY(1) RDY(2) Data OE#, (stays low) CE# Notes: 1. RDY active with data (DQ8 = 0 in the Configuration Register). 2. RDY active one clock ...
Page 92
Data AVD# OE# CLK Wait State Configuration Register Setup: DQ13, DQ12, DQ11 = “111” ⇒ Reserved DQ13, DQ12, DQ11 = “110” ⇒ Reserved DQ13, DQ12, DQ11 = “101” ⇒ 5 programmed, 7 total DQ13, DQ12, DQ11 = “100” ⇒ 4 ...
Page 93
Erase and Programming Performance Parameter 64 Kword Sector Erase Time 16 Kword Chip Erase Time Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time Chip Programming Time (Note 3) ...
Page 94
Pseudo SRAM with Page & Burst FEATURES Fast Access Cycle Time t =70ns max CE 8 words Page Read Access Capability t =20ns max PAA Burst Read/Write Access Capability t =11ns max AC ...
Page 95
FUNCTION TRUTH TABLE Asynchronous Operation (Page Mode) Mode Note CE2pS2 CE#1pS Standby H (Deselect) Output Disable *1 Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) H Page Read No Write Write (Upper Byte) Write (Lower Byte) ...
Page 96
FUNCTION TRUTH TABLE (Continued) Synchronous Operation (Burst Mode) Mode Note CE2 Standby (Deselect) Start *1 Address Latch Advance Burst Read to *1 Next Address Burst Read *1 Suspend H Advance Burst Write to *1 Next Address Burst Write *1 Suspend ...
Page 97
STATE DIAGRAM Initial/Standby State Power Up Pause Time Power Down CE2=H CE2=L Standby Asynchronous Operation CE#1=L & WE#=L Write Byte Control Synchronous Operation CE#1=H CE#1=H Write Suspend WE#=H WE#=L Write ADV# Low Pulse Note: Assuming all the parameters specified in ...
Page 98
FUNCTIONAL DESCRIPTION This device supports asynchronous page read & normal write operation and syn- chronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as user configuable option. ...
Page 99
FUNCTIONAL DESCRIPTION (Continued) Address Key The address key has the following format. Address Register Pin Name A22-A21 — A20-A19 PS A18-A16 BL A15 M A14-A12 RL A11 BS A10 — A6-A0 — Notes *1: ...
Page 100
FUNCTIONAL DESCRIPTION (Continued) Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and mains low power idle state as long as CE2 is kept low. CE2 High ...
Page 101
FUNCTIONAL DESCRIPTION (Continued) Burst Read/Write Operation Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. Configuration Register Set is required to perform burst read & write operation after power-up. Once CR Set sequence ...
Page 102
FUNCTIONAL DESCRIPTION (Continued) CLK Input Function The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. The CLK input increments device internal address counter and the valid edge of ...
Page 103
FUNCTIONAL DESCRIPTION (Continued) Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation set through CR Set sequence after power-up. Once specific ...
Page 104
FUNCTIONAL DESCRIPTION (Continued) Address Latch by ADV# The ADV# indicates valid address presence on address inputs. During synchronous burst read/write operation mode, all the address are determined on the positive edge of ADV# when CE#1=L. The specified minimum value of ...
Page 105
Write Control The device has two type of WE# signal control method, "WE# Level Control" and "WE# Single Clock Pulse Control", for synchronous write operation configured through CR set sequence. CLK ADDRESS ADV# CE#1 WE# Level Control WE# ...
Page 106
FUNCTIONAL DESCRIPTION (Continued) Burst Read Suspend Burst read operation can be suspended by OE# High pulse. During burst read operation, OE# brought to High suspends burst read operation. Once OE# is brought to High with the specified set up time ...
Page 107
FUNCTIONAL DESCRIPTION (Continued) Burst Read Termination Burst read operation can be terminated by CE#1 brought to High set on Continuous, burst read operation is continued endless unless terminated by CE#1= inhibited to terminate burst read ...
Page 108
ABSOLUTE MAXIMUM RATINGS (See WARNING below.) Parameter Voltage of V Supply Relative Voltage of V Supply Relative to V DDQ Voltage at Any Pin Relative to V Short Circuit Output Current Storage Temperature WARNING: Semiconductor devices can ...
Page 109
DC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted) Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level V Power Down DD Current V Standby DD Current V Active Current DD V Page Read ...
Page 110
AC CHARACTERISTICS (Under Recommended Operating Conditions unless otherwise noted) ASYNCHRONOUS READ OPERATION (PAGE MODE) Parameter Read Cycle Time CE#1 Access Time OE# Access Time Address Access Time ADV# Access Time LB#, UB# Access Time Page Address Access Time Page Read ...
Page 111
AC CHARACTERISTICS (Continued) ASYNCHRONOUS WRITE OPERATION Parameter Write Cycle Time Address Setup Time ADV# Low Pulse Width Address Hold Time from ADV# High CE#1 Write Pulse Width WE# Write Pulse Width LB#, UB# Write Pulse Width CE#1 Write Recovery Time ...
Page 112
AC CHARACTERISTICS (Continued) SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE) Parameter RL=5 Clock Period RL=4 RL=3 Clock High Time Clock Low Time Clock Rise/Fall Time Notes *1: Clock period is defined between valid clock edge. *2: Clock rise/fall time is ...
Page 113
AC CHARACTERISTICS (Continued) SYNCHRONOUS READ OPERATION (BURST MODE) Parameter Burst Read Cycle Time CLK Access Time Output Hold Time from CLK CE#1 Low to WAIT# Low OE# Low to WAIT# Low ADV# Low to WAIT# Low CLK to WAIT# Valid ...
Page 114
AC CHARACTERISTICS (Continued) SYNCHRONOUS WRITE OPERATION (BURST MODE) Parameter Burst Write Cycle Time Data Setup Time to Clock Data Hold Time from CLK WE# Low Setup Time to 1st Data In UB#, LB# Setup Time for Write WE# Setup Time ...
Page 115
AC CHARACTERISTICS (Continued) POWER DOWN PARAMETERS Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE#1 High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE#1 High Hold ...
Page 116
AC CHARACTERISTICS (Continued) AC TEST CONDITIONS Symbol Description V Input High Level IH V Input Low Level IL V Input Timing Measurement Level REF Input Transition t T Time AC MEASUREMENT OUTPUT LOAD CIRCUIT V CCPS 0.1µ ...
Page 117
TIMING DIAGRAMS Asynchronous Read Timing #1-1 (Basic Timing). ADDRESS ADV# Low t ASC CE#1 OE# LB# / UB# t OLZ DQ (Output) Note: This timing diagram assumes CE2=H and WE#=H. Asynchronous Read Timing #1-2 (Basic Timing) ADDRESS VALID ADDRESS t ...
Page 118
TIMING DIAGRAMS (Continued) Asynchronous Read Timing #2 (OE# & Address Access) ADDRESS ADDRESS VALID t CE#1 Low t ASO OE# LB# / UB# DQ (Output) Notes:This timing diagram assumes CE2=H, ADV#=L and WE#=H. Asynchronous Read Timing #3 (LB# / UB# ...
Page 119
TIMING DIAGRAMS (Continued) Asynchronous Read Timing #4 (Page Address Access after CE#1 Control Access) ADDRESS (A22-A3 ADDRESS ADDRESS VALID (A2-A0) t ASC ADV# CE OE# LB# / UB# t CLZ DQ (Output) VALID DATA OUTPUT (Normal ...
Page 120
TIMING DIAGRAMS (Continued) Asynchronous Write Timing #1-1 (Basic Timing) ADDRESS ADV# Low WE# LB#, UB# t OHCL OE# DQ (Input) Notes:This timing diagram assumes CE2=H and ADV#=L. Asynchronous Write Timing #1-2 (Basic Timing) ADDRESS ADDRESS ...
Page 121
TIMING DIAGRAMS (Continued) Asynchronous Write Timing #2 (WE# Control) ADDRESS t OHAH CE#1 Low t AS WE# LB#, UB# t OES OE# t OHZ DQ (Input) Note: This timing diagram assumes CE2=H and ADV#=L. Asynchronous Write Timing #3-1 (WE# / ...
Page 122
TIMING DIAGRAMS (Continued) Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control) ADDRESS CE#1 Low WE LB# UB# DQ0-7 (Input) DQ8-15 (Input) Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H. Asynchronous Write Timing #3-3 ...
Page 123
TIMING DIAGRAMS (Continued) Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control) ADDRESS CE#1 Low WE LB# DQ1-8 (Input UB# DQ9-16 (Input) Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H. June 28, ...
Page 124
TIMING DIAGRAMS (Continued) Asynchronous Read / Write Timing #1-1 (CE#1 Control) ADDRESS t t CHAH AS CE WE# UB#, LB# t OHCL OE# t CHZ READ DATA OUTPUT Notes *1: This timing diagram assumes CE2=H ...
Page 125
TIMING DIAGRAMS (Continued) Asynchronous Read / Write Timing #2 (OE#, WE# Control) ADDRESS t OHAH CE#1 Low t AS WE# t OES UB#, LB# OE# t OHZ READ DATA OUTPUT Notes *1: This timing diagram assumes CE2=H ...
Page 126
TIMING DIAGRAMS (Continued) Clock Input Timing CLK t CK Notes *1: Stable clock input must be required during CE#1=L. * defined between valid clock edge defined between V CKT Address Latch Timing (Synchronous Mode) ...
Page 127
TIMING DIAGRAMS (Continued) Synchronous Read Timing #1 (OE# Control) RL=5 CLK ADDRESS Valid t t ASVL AHV t VSCK t CKVH ADV# t VPL t ASCL CE#1 t CLCK OE# High WE# LB#, UB# WAIT# High-Z t OLTL DQ High-Z ...
Page 128
TIMING DIAGRAMS (Continued) Synchronous Read Timing #2 (CE#1 Control) RL=5 CLK ADDRESS Valid t t ASVL AHV t VSC t CKVH ADV# t VPL t ASCL CE#1 t CLCK OE# High WE# LB#, UB# WAIT# t CLTL DQ t CLZ ...
Page 129
TIMING DIAGRAMS (Continued) Synchronous Read Timing #3 (ADV# Control) RL=5 CLK ADDRESS Valid t t ASVL AHV t VSCK t CKVH ADV# t VPL CE#1 Low Low OE# High WE# LB#, UB# t VLTL RDY DQ Note: This timing diagram ...
Page 130
TIMING DIAGRAMS (Continued) Synchronous Write Timing #1 (WE# Level Control) RL=5 CLK ADDRESS Valid t t ASVL AHV t VSCK t CKVH ADV# t VPL t ASCL CE#1 t CLCK High OE# WE LB#, UB# RDY High-Z t ...
Page 131
TIMING DIAGRAMS (Continued) Synchronous Write Timing #2 (WE# Single Clock Pulse Control) RL=5 CLK ADDRESS Valid t t ASVL AHV t VSCK t CKVH ADV# t VPL t ASCL CE#1 t CLCK High OE WSCK CKWH WE# t ...
Page 132
TIMING DIAGRAMS (Continued) Synchronous Write Timing #3 (ADV# Control) RL=5 CLK ADDRESS Valid t t ASVL AHV t VSCK t CKVH ADV# t VPL CE#1 High OE# WE LB#, UB# High WAIT# DQ Note: This timing diagram assumes ...
Page 133
TIMING DIAGRAMS (Continued) Synchronous Write Timing #4 (WE# Level Control, Single Write) RL=5 CLK ADDRESS Valid t t ASVL t VSCK t CKVH ADV# t VPL t ASCL CE#1 t CLCK High OE# WE LB#, UB# WAIT# High-Z ...
Page 134
TIMING DIAGRAMS (Continued) Synchronous Read to Write Timing #1(CE#1 Control) CLK ADDRESS t ASVL ADV# t VHVL t t CKCLH ASCL CE OE# WE# t CKBH LB#, UB# WAIT# t CHZ BL-1 BL ...
Page 135
TIMING DIAGRAMS (Continued) Synchronous Read to Write Timing #2(ADV# Control) CLK ADDRESS t ASVL ADV# t VHVL CE#1 t CKOH OE# WE# t CKBH LB#, UB# WAIT# t OHZ BL CKQX CKQX ...
Page 136
TIMING DIAGRAMS (Continued) Synchronous Write to Read Timing #1 (CE#1 Control) CLK ADDRESS ADV# t CKCLH CE#1 OE# WE# t CKBH LB#, UB# WAIT DSCK DSCK CHTZ BL DHCK DHCK Note: ...
Page 137
TIMING DIAGRAMS (Continued) Synchronous Write to Read Timing #2 (ADV# Control) CLK ADDRESS ADV# Low CE#1 OE# t CKWH WE# t CKBH LB#, UB# WAIT DSCK DSCK WHTZ BL DHCK DHCK ...
Page 138
TIMING DIAGRAMS (Continued) POWER-UP Timing #1 CE#1 *2 CE2 * IOPS 0V V CCPS 0V Notes *1: V shall be applied and reach the specified minimum level prior to V DDQ *2: The both of CE#1 and CE2 ...
Page 139
TIMING DIAGRAMS (Continued) POWER DOWN Entry and Exit Timing CE#1 CE2 t CSP DQ Power Down Entry Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down ...
Page 140
TIMING DIAGRAMS (Continued) Configuration Register Set Timing #1 (Asynchronous Operation ADDRESS MSB* MSB CE#1 OE# WE# LB#, UB# RDa DQ* 3 Cycle #1 Cycle #2 Notes *1: The all address inputs must be High from ...
Page 141
TIMING DIAGRAMS (Continued) Configuration Register Set Timing #2 (Synchronous Operation) CLK ADDRESS MSB MSB t t RCB ADV# t TRB CE#1 OE# WE# LB#, UB# RL RL-1 RDa DQ Cycle#1 Cycle#2 Notes *1: The all address inputs must be High ...
Page 142
Revision Summary Revision A (April 27, 2004) Initial release. Revision A+1 (June 28, 2004) Modify Colophon & Company name. Trademarks and Notice The products described in this document are designed, developed and manufactured as contemplated for general use, including without ...