9DB102BFILF IDT [Integrated Device Technology], 9DB102BFILF Datasheet - Page 5

• Manufacturer Part Number: 9DB102BFILF
• Description: Two Output Differential Buffer for PCIe Gen1 & Gen2
• Manufacturer: IDT [Integrated Device Technology]

IDT
T
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
Electrical Characteristics - PLL Parameters
PLL Jitter Peaking
PLL Jitter Peaking
A
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
PLL Bandwidth
PLL Bandwidth
®
Jitter, Phase
= Tambient; Supply Voltage V
Two Output Differential Buffer for PCIe Gen1 & Gen2
Group
Parameter
t
j
j
peak-hibw
peak-lobw
pll
jphasePLL
pll
LOBW
HIBW
DD
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
= 3.3 V +/-5%
PCIe Gen 1 phase jitter
PCIe Gen 2 jitter
PCIe Gen 2 jitter
PCIe Gen 2 jitter
(PLL_BW = 1)
(PLL_BW = 0)
(PLL_BW = 1)
(PLL_BW = 0)
(1.5 - 22 MHz)
(PLL_BW=1)
(PLL_BW=0)
Description
5
Min
0.4
0
0
2
Typ
2.5
0.5
2.7
2.2
1.3
40
1
1
Max
108
2.5
3.1
3.1
2
3
1
3
ps rms
ps rms
ps rms
852
Units
MHz
MHz
dB
dB
ps
REV K 04/01/10
Notes
1,2,3
1,2,3
1,2,3
1,2,3
1,4
1,4
1,5
1,5