IDT72V70200PF IDT, Integrated Device Technology Inc, IDT72V70200PF Datasheet - Page 4

• Manufacturer Part Number: IDT72V70200PF
• Description: IC DGTL SW 512X512 3.3V 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70200PF

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V70200PF

N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
2.048 Mb/s and are arranged in 125 s wide frames, which contain 32 channels
respectively. The data rates on input and output streams are identical.
slots on a per channel basis allowing for transfer of control and status information.
The IDT72V70200 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS
formats.
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 8.
RX inputs for diagnostic purposes.
DATA AND CONNECTION MEMORY
to-parallel converters and stored sequentially in the data memory. The 8KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 512 bytes.
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 10. Once the source address bits are programmed by the
microprocessor, the contents of the data memory at the selected address are
transferred to the parallel-to-serial converters and then onto a TX output stream.
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
The IDT72V70200 is capable of switching 512 x 512, 64 Kbit/s PCM or
The serial input streams of the IDT72V70200 can have a bit rate of
In Processor Mode, the microprocessor can access input and output time-
With the variety of different microprocessor interfaces, IDT72V70200 has
The frame offset calibration function allows users to measure the frame offset
The internal loopback allows the TX output data to be looped around to the
A functional Block Diagram of the IDT72V70200 is shown in Figure 1.
The received serial data is converted to parallel format by internal serial-
Data to be output on the serial streams (TX0-15) may come from either the
In the Connection Mode, the addresses of the input source data for all output
By having the each location in the connection memory specify an input
In Processor Mode, the microprocessor writes data to the connection
12
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or GCI
4
serial converter one time-slot before it is to be output. This data will be output
on the TX streams in every frame until the data is changed by the microprocessor.
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70200 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 3 and 5).
SERIAL DATA INTERFACE TIMING
data rates of 2.048 Mb/s, the master clock (CLK) must be at 4.096 MHz. The
input and output stream data rates will always be identical.
IDT72V70200 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS
edge of the master clock marks a bit boundary and the data is clocked in on the
rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In
GCI format, every second rising edge of the master clock marks the bit boundary
and data is clocked in on the falling edge of CLK at three quarters of the way
into the bit cell, see Figure 8.
INPUT FRAME OFFSET SELECTION
streams to be offset with respect to the output stream channel alignment (i.e. F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
frame input offset registers (FOR). The maximum allowable skew is +4.5 master
clock (CLK) periods forward with resolution of ½ clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 8 and 9 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
different data input delays with respect to the frame pulse F0i.
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
As the IDT72V70200 can be used in a wide variety of applications, the device
If an output channel is set to a high-impedance state through the connection
The connection memory data can be accessed via the microprocessor
The master clock frequency must always be twice the data rate. For serial
The input 8 KHz frame pulse can be in either ST-BUS
Input frame offset selection allows the channel alignment of individual input
Each input stream can have its own delay offset value by programming the
The IDT72V70200 provides the frame evaluation (FE) input to determine
A measurement cycle is started by setting the start frame evaluation (SFE)
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or GCI. In ST-BUS
COMMERCIAL TEMPERATURE RANGE
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format, every second falling
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or GCI format. The
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