UAA3522 PHILIPS [NXP Semiconductors], UAA3522 Datasheet - Page 8

• Manufacturer Part Number: UAA3522
• Description: Low power dual-band GSM transceiver with an image rejecting front-end
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
The synthesizer, receiver and transmitter cannot all be on
at the same time. Table 1 shows which parts of the device
are enabled (on) or disabled (off) in each mode.
Table 1 Operating modes
The synthesizer includes the oscillators and LO buffers
common to the receive and transmit sections. The receiver
includes the RF section and the I/Q demodulator. When
the receiver is on, the LNA can be switched off to allow
DC offset compensation to be performed. The RF section
can also be switched off for DCS applications. See Section
“Receiver power status control”.
R
2000 Feb 18
MODE
Idle
SYN
RX
TX
ECEIVER POWER STATUS CONTROL
DC offset compensation: This feature allows the DC
offset of the receiver output to be set accurately. When
the receiver is on, the LNA can be switched off to isolate
the antenna input from the I/Q demodulator input.
The offset at the I and Q outputs can be independently
reduced to less than 50 mV by adequately programming
two 5-bit data registers, see Table 4 “Register bit
allocation”. The LNA is switched on or off by the status
of bit LNA (see Table 2).
Disabling RF section: For DCS applications, the RF
section can be disabled in RX mode. The same
IF circuits are used for both GSM and DCS applications
to avoid duplication. For DCS applications using the
UAA2077XM, for example, the RF section of the
UAA3522HL does not have to be powered on.
The RF section is enabled or disabled by the status of
bit RF when the RX mode is activated (see Table 3).
Low power dual-band GSM transceiver
with an image rejecting front-end
SYNTHESIZER RECEIVER TRANSMITTER
off
on
on
on
POWER STATUS
off
off
on
off
off
off
off
on
8
Table 2 Bit LNA status
Table 3 Bit RF status
Programming
S
A simple 3-wire unidirectional serial bus is used for
programming the IC. The lines are called DATA, CLK
and EN (enable). Programming data is sent to the IC in
bursts which are separated from each other by EN.
Programming clock edges are ignored until EN goes
active LOW. The data is loaded into the addressed register
when EN returns inactive HIGH, and when the CLK is in
either state, without affecting the data in the register.
The register only holds the last 18 bits that are serially
clocked into the IC.
Additional leading bits are ignored, and no check is made
on the number of clock pulses received. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always accept new programming data even
when both synthesizers are powered-off.
D
Data is loaded into the register with the most significant bit
(MSB) first. The first 14 bits are data, while the last 4 bits
are the register address. The address bits are decoded on
the rising edge of EN. This internally generates a load
pulse to store the data in the addressed register.
To ensure that data loads correctly after the device has
powered-up, EN should be held LOW and only taken HIGH
after the appropriate register has been loaded.
The EN pulse is inhibited during the period when data is
read by the frequency dividers to prevent divider ratio data
from being read incorrectly. This state is guaranteed by
always allowing for a minimum EN pulse width after data
transfer.
ERIAL PROGRAMMING BUS
ATA FORMAT
BIT LNA STATUS
BIT RF STATUS
0
1
1
0
RECEIVER RF SECTION
POWER STATUS OF BIT
POWER STATUS OF
Objective specification
UAA3522HL
IN RX MODE
on (GSM)
off (DCS)
LNA
off
on