PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 65

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

No
Bit
0
1
2
3
4
5
6
7
6 0 Serial Ports
Bit 6 This bit is the Break Control bit It causes a break
Note that this feature enables the CPU to alert a terminal If
the following sequence is used no erroneous characters
will be transmitted because of the break
Note 1 Bit 0 is the least significant bit It is the first bit serially transmitted or received
Note 2 These bits are always 0 in the NS16450 Mode
Note 3 This bit no longer has a pin associated with it
DLAB
Receiver Transmitter
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
A0 –2
Register
(Note 1)
Buffer
(Read
Only)
RBR
condition to be transmitted to the receiving UART
When it is set to 1 the serial output (SOUT) is forced
to the Spacing state (0) The break is disabled by set-
ting bit 6 to 0 The Break Control bit acts only on
SOUT and has no effect on the transmitter logic
1 Wait for the transmitter to be idle (TEMT
2 Set break for the appropriate amount of time If the
e
e
transmitter will be used to time the break duration
then check that TEMT
Break Control bit
0
0
DLAB
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
A0 – 2
Register
Holding
(Write
Only)
THR
e
e
0
0
TABLE 6-2 PC87332 Register Summary for an Individual UART Channel
Transmitter
Line Status
(Continued)
DLAB
A0– 2
Interrupt
Received
Register
Available
Receiver
MODEM
Interrupt
Register
Interrupt
Interrupt
Interrupt
Enable
Holding
Enable
Enable
Enable
Enable
Empty
Status
Data
IER
0
0
0
0
e
e
1
0
e
1 before clearing the
Interrupt
Register
Interrupt
Interrupt
Interrupt
Interrupt
Pending
(Note 2)
Enabled
(Note 2)
Enabled
(Note 2)
Ident
(Read
FIFOs
FIFOs
Only)
‘‘0’’ if
IIR
Bit
Bit
Bit
ID
ID
ID
2
0
0
Reserved
Reserved Even Parity
Reserved
Register
Control
Enable
Trigger
Trigger
(Write
RCVR
RCVR
RCVR
(MSB)
Only)
Reset
Reset
XMIT
(LSB)
FIFO
FIFO
FIFO
FIFO
FCR
e
2
1)
Access Bit
Number of
Register Address
Register
Stop Bits
Control
(DLAB)
Length
Length
Enable
Divisor
Select
Select
Select
Break
Word
Word
Parity
Parity
Latch
Stick
Line
LCR
Bit 0
Bit 1
Set
3
65
Bit 7 This bit is the Divisor Latch Access Bit (DLAB) It must
Register
MODEM
Terminal
Control
Request
(Note 3)
to Send
Enable
Ready
(DTR)
(RTS)
Out 1
MCR
Loop
Data
IRQ
Bit
4
0
0
0
be set high (logic 1) to access the Divisor Latches of
the Baud rate Generator during a Read or Write opera-
tion or to have the Baud Out (BOUT) signal appear on
the BOUT pin It must be set low (logic 0) to access
any other register
3 Clear break when normal transmission has to be
During the break the Transmitter can be used as a
character timer to accurately establish the break dura-
tion by sending characters and monitoring THRE and
TEMT
restored
Transmitter
Transmitter
Register
Framing
Interrupt
Register
Overrun
(Note 2)
Holding
(THRE)
(TEMT)
Error in
Status
Ready
Empty
RCVR
Break
Parity
Error
Error
Error
FIFO
Line
Data
(DR)
(OE)
LSR
(PE)
(FE)
(BI)
5
Edge Ring
Register
MODEM
Indicator
Indicator
to Send
Clear to
Trailing
Status
Carrier
Detect
Carrier
Detect
Ready
Ready
(DSR)
(DCD)
(CTS)
Delta
Clear
Delta
Delta
MSR
Send
Data
Data
Data
Ring
Data
(RI)
Set
Set
6
Register
Scratch
SCR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pad
7
DLAB
A0–2
Divisor
(LSB)
Latch
DLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
e
e
0
1 DLAB
A0–2
Divisor
(MSB)
Latch
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
DLM
Bit 8
Bit 9
e
e
1
1