PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 76

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

7 0 Parallel Port
7 6 EXTENDED CAPABILITIES PARALLEL PORT (ECP)
7 6 1 Introduction
The ECP support includes a 16-byte FIFO that can be con-
figured for either direction command data FIFO tags (one
per byte) a FIFO threshold interrupt for both directions
FIFO empty and full status bits automatic generation of
strobes (by hardware) to fill or empty the FIFO transfer of
commands and data and a Run Length Encoding (RLE) ex-
panding (decompression) as explained below
The Extended Capabilities Port (ECP) is enabled when bit 2
of PCR is 1 Once enabled its mode is controlled via the
mode field of ECR bits 5 6 7 of the ECR register
The ECP has ten registers See Table 7-7
The AFIFO CFIFO DFIFO and TFIFO registers access the
same ECP FIFO The FIFO is accessed at Base
Base
register
The FIFO can be accessed by host DMA cycles as well as
host PlO cycles
When DMA is configured and enabled (bit 3 of ECR is 1 and
bit 2 of ECR is 0) the ECP automatically (by hardware) is-
sues DMA requests to fill the FIFO (in the forward direction
when bit 5 of DCR is 0) or to empty the FIFO (in the back
Note The Base address is stored in bits A2–A9 It is 278h 378h or 3BCh as specified in the FAR register
A10
0
0
0
0
1
1
1
1
1
1
a
400h depending on the mode field of ECR and the
A1
0
0
0
1
0
0
0
0
0
1
A0
0
0
1
0
0
0
0
0
1
0
(Continued)
Address
Offset
0
0
1
2
3
3
3
3
4
5
Register
DATAR
AFIFO
DSR
DCR
CFIFO
DFIFO
TFIFO
CNFGA
CNFGB
ECR
TABLE 7-7 ECP Registers Summary
a
000h or
Access
R W
R W
R W
R W
R W
W
W
R
R
R
76
ward direction when bit 5 of DCR is 1) All DMA transfers are
to or from these registers The ECP does not assert a DMA
request for more than 32 consecutive DMA cycles The ECP
stops requesting DMA when Terminal Count TC is detect-
ed during an ECP DMA cycle
A write operation to a full FIFO or a read operation from an
empty FIFO are ignored The written data is lost and the
read data is undefined The FIFO empty and full status bits
are not affected by such an access
Some registers are not accessible in all modes of operation
or may be accessed in one direction only Accessing a non-
accessible register has no effect Data read is undefined
data written is ignored the FIFO does not update The
PC87334 Parallel Port registers (DTR STR and CTR) are
not accessible when ECP is enabled
To improve noise immunity in ECP cycles the state ma-
chine does not examine the control handshake response
lines until the data has had time to switch
In ECP mode
DATAR replaces DTR of SPP EPP
DSR replaces SPR of SPP EPP
DCR replaces CTR of SPP EPP
A detailed description of the various modes follow in Sec-
tions 7 8– 7 11
Size
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
ECR (5– 7)
Mode
000 001
ALL
ALL
ALL
011
010
011
110
111
111
Parallel Port Data Register
ECP Address FIFO
Status Register
Control Register
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Function