M72DW64000B90ZT STMICROELECTRONICS [STMicroelectronics], M72DW64000B90ZT Datasheet - Page 6

• Manufacturer Part Number: M72DW64000B90ZT
• Description: 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M72DW64000B
SIGNAL DESCRIPTION
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). Address lines A0-A19
are common inputs for the Flash Memory and
PSRAM components. Address line A20-A21 are
inputs for the Flash Memory component. The Ad-
dress Inputs select the cells in the memory array
to access during Bus Read operations. During Bus
Write operations they control the commands sent
to the Command Interface of the internal state ma-
chine. The Flash memory is accessed through the
Chip Enable (
while the PSRAM is accessed through two Chip
Enable signals (E1
able signal (W).
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
V
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–
1). When BYTE is High, V
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, V
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Flash-1 Chip Enable (E
put activates the memory to which it is attached,
allowing Bus Read and Bus Write operations to be
performed. When Chip Enable is High, V
er pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the Flash Memory
and PSRAM components.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the Flash Memory and
PSRAM components.
V
Protect pin provides two functions. The V
tion allows the Flash memory to use an external
high voltage power supply to reduce the time re-
6/19
IH
PP/
. When BYTE is Low, V
Write Protect (V
E
F
IL
) and Write Enable (W) signals,
, this pin behaves as an address
S
and E2
PP
/WP). The
F
). The Chip Enable in-
IH
IL
S
, this pin behaves as
, these pins are not
) and the Write En-
V
IH
PP
PP
, all oth-
/Write
func-
quired for Program operations. This is achieved
by bypassing the unlock cycles and/or using the
multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
When V
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while V
at V
When V
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When V
ory automatically enters the Unlock Bypass mode.
When V
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t
more details.
Never raise V
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The V
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
tween the V
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I
Reset/Block Temporary Unprotect (RP
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
most boot blocks will remain protected even if RP
is at V
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
goes High, V
Read and Bus Write operations after t
PLPX
IH
ID
to V
. After Reset/Block Temporary Unprotect
VHVPP
.
PP
ID
PP
PP
PP
.
PP
PP
PP
/Write Protect pin must not be left floating
/Write Protect is Low, even when RP
/Write Protect is raised to V
/Write Protect is High, V
/Write Protect returns to V
/Write Protect is Low, V
and from V
. See the M29DW640D datasheet for
IH
PP
PP
PP
, the memory will be ready for Bus
/Write Protect pin and the V
/WP is at V
/Write Protect to V
PP
PP
to V
IL
, then the two outer-
.
IH
must be slower
IH
IL
IL
, the memory
, the memory
IH
PP
, for at least
PP
or V
the mem-
from any
F
PHEL
PP
). The
IL
from
nor-
F
SS
or
is
F