M72DW64000B90ZT STMICROELECTRONICS [STMicroelectronics], M72DW64000B90ZT Datasheet - Page 7

• Manufacturer Part Number: M72DW64000B90ZT
• Description: 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

t
M29DW640D datasheet for more details.
Holding RP
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the Flash memory is performing a Program
or Erase operation. During Program or Erase op-
erations Ready/Busy is Low, V
high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
Flash memory. When Byte/Word Organization Se-
lect is Low, V
when it is High, V
mode.
PSRAM Chip Enable inputs (E1
Chip Enable inputs activate the PSRAM control
logic, input buffers and decoders. E1
E2
power consumption to the standby level, whereas
E2
power consumption to the Power-down level, re-
RHEL
PHPHH
P
P
at V
at V
,
.
IL
whichever
IH
deselects the memory and reduces the
F
deselects the memory, reducing the
at V
IL
, the Flash memory is in x8 mode,
ID
IH
, the Flash memory is in x16
will temporarily unprotect the
IH
occurs
to V
ID
must be slower than
OL
last.
P
. Ready/Busy is
, E2
P
P
at V
See
). The
IH
with
the
gardless of the level of E1
be used to control writing to the PSRAM memory
array, while W
set E
same time.
PSRAM Upper Byte Enable (UB
Byte Enable input enables the upper byte for
PSRAM (DQ8-DQ15). UB
PSRAM Lower Byte Enable (LB
Byte Enable input enables the lower byte for
PSRAM (DQ0-DQ7). LB
V
vides the power supply for Flash memory opera-
tions (Read, Program and Erase).
The Command Interface is disabled when the
V
age, V
from accidentally damaging the data during power
up, power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I
V
vides the power supply for the PSRAM.
V
voltage measurements in the Flash and PSRAM
chips.
CCF
CCF
CCP
SS
Ground. V
CCF
F1
Supply Voltage (2.7 to 3.3V). V
Supply Voltage is less than the Lockout Volt-
Supply Voltage (2.7 to 3.3V). V
LKO
at V
Supply Voltage pin and the V
. This prevents Bus Write operations
IL,
P
E1
remains at V
SS
P
CC3
is the ground reference for all
at V
.
P
IL
P
P
is active low.
. E1
and E2
is active low.
IL.
P
M72DW64000B
It is not allowed to
and E2
P
P
). The Lower
P
). The Upper
at V
SS
CCF
CCP
P
IH
can also
Ground
at the
pro-
pro-
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