AM49BDS640AHD8I SPANSION [SPANSION], AM49BDS640AHD8I Datasheet
AM49BDS640AHD8I
Related parts for AM49BDS640AHD8I
AM49BDS640AHD8I Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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ADVANCE INFORMATION Am49BDS640AH Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode 64 Megabit ( 16-Bit) Flash Memory, and 16 Mbit ( 16-Bit) pSRAM DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single 1.8 ...
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Burst Suspend/Resume — Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state ...
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GENERAL DESCRIPTION The Am49BDS640AH Mbit, 1.8 Volt-only, simulta- neous Read/Write, Burst Mode Flash memory device, orga- nized as 4,194,304 words of 16 bits each. This device uses a single V ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . ...
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 44 Figure 8. Maximum Negative Overshoot Waveform ....................... 44 Figure 9. Maximum Positive ...
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PRODUCT SELECTOR GUIDE Part Number Burst Frequency Speed Option Max Initial Synchronous Access Time Reduced Wait-state Handshaking; Even Address Max Initial Synchronous Access Time Reduced Wait-state Handshaking; Odd Address; ...
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BLOCK DIAGRAM RDY V Buffer IO WE# State RESET# Control WP# Command ACC Register CE# OE Detector Burst AVD# State CLK Control A21–A0 December 5, 2003 I ...
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BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT A21–A0 WP# A21–A0 ACC STATE RESET# CONTROL WE# & CE# COMMAND AVD# REGISTER RDY DQ15–DQ0 A21–A0 A21–A0 A21– ...
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CONNECTION DIAGRAM ADV WP ...
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PIN DESCRIPTION A19– Address Inputs (Common) A21–A20 = 2 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (SRAM) CE2s = ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49BDS640A DEVICE NUMBER/DESCRIPTION Am49BDS640AH 64 Megabit ( 16-Bit) CMOS Flash Memory, Simultaneous Read/Write, Burst Mode Flash ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory ...
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When the device first powers up enabled for asyn- chronous read operation. Prior to entering burst mode, the system should deter- mine how many wait states are desired for the initial ...
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Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh),” on page 53, Figure 21, “Reduced Wait-state Handshake Burst SuspendResume at address 3Fh (or offset from 3Fh by a multiple of 64),” on ...
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“bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector the “DC Characteristics” section on ...
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Table 3. Am49BDS640AH Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21–A12 SA0 0000000000 SA1 0000000001 SA2 0000000010 SA3 0000000011 SA4 0000000100 SA5 0000000101 SA6 0000000110 SA7 0000000111 SA8 0000001XXX SA9 0000010XXX SA10 0000011XXX ...
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erate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using ...
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PPB are needed e.g. to allow new system code to be downloaded changes are needed then the boot code can set the PPB Lock to disable any further changes to the ...
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grammed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs ...
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Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for ns. The auto- ...
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START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word SecSi sector ...
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Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP# pin and overrides the previ- ously discussed Sector Protection/Unprotection ...
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Addresses Data 1Bh 0017h 1Ch 0019h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 0009h 22h 0000h 23h 0004h 24h 0000h 25h 0004h 26h 0000h Addresses Data 27h 0018h 28h 0001h 29h ...
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Table 9. Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 000Ch 46h 0002h 47h 0001h 48h 0000h 49h 0007h 4Ah 00E7h 4Bh 0001h 4Ch ...
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COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 15, “Command Definitions,” ...
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Table 10. Programmable Wait State Settings Total Initial Access A14 A13 A12 ...
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Read Mode Configuration The device supports four different read modes: contin- uous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances ...
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Address BIt Function Settings (Binary) Set Device 0 = Synchronous Read (Burst Mode) Enabled A19 Read Mode 1 = Asynchronous Mode (default RDY active one clock cycle before data A18 RDY ...
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represents the sector address. The device ID is read in three cycles. Description Address Manufacturer (BA) + 00h ID Device ID, (BA) + 01h Word 1 Device ID, (BA) + 0Eh Word ...
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The device offers accelerated program operations through the ACC input. When the system asserts V on this input, the device automatically enters the Unlock Bypass mode. The system may then write the t ...
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The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. ...
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are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? ...
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SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which pre- vents the SecSi sector memory from being cleared. If the SecSi Sector ...
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out margin, the erase command should be reissued to improve the program margin the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If ...
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Command Definitions Command Sequence (Note 1) Addr Data Addr Data Addr Data Addr Asynchronous Read (Note 7) 1 Reset (Note 8) 1 Manufacturer ID 4 Device ID 6 Sector Lock Verify (Note 4 ...
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Command Sequence (Note 1) Addr Data Addr Data Addr Data Addr PPB Program (Notes 18, 6 19, 21) PPB All PPB Erase (Notes 6 Command 18, 19, 22, 24) s PPB Status (Note ...
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14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 17, “Write Operation Status,” on page 43 and ...
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RDY: Ready The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the ...
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START Read Byte (DQ7-DQ0) Address = VA Read Byte (DQ7-DQ0) Address = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice (DQ7-DQ0) Adrdess = VA No DQ6 = ...
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device is and the system reads programming, at any address address within a sector selected for erasure, actively erasing address within sectors not selected for erasure ...
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DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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CHARACTERISTICS CMOS COMPATIBLE Parameter Description I Input Load Current LI I Output Leakage Current Active burst Read Current CCB Non-active Output IO1 IO V Active Asynchronous ...
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TEST CONDITIONS Device Under Test C L Figure 10. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted SWITCHING WAVEFORMS V IO All Inputs and Outputs 0.0 V Figure 11. ...
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CHARACTERISTICS V Power-up CC Parameter Description t V Setup Time VCS Setup Time VIOS IO t RESET# Low Hold Time RSTH RESET# December ...
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CHARACTERISTICS Synchronous/Burst Read Parameter JEDEC Standard Description Latency (Even address in Reduced wait-state t IACC Handshake mode) Latency (Standard Handshake or Odd t address in Reduced wait-state Handshake IACC mode Burst Access ...
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CHARACTERISTICS t CES CE#f 1 CLK t AVC AVD# t AVD t ACS Addresses Aa t ACH Data OE Hi-Z RDY Notes: 1. Figure shows total number of wait states ...
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CHARACTERISTICS t CAS CE# 1 CLK t AVC AVD# t AVD t AAS Addresses Aa t AAH Data OE Hi-Z RDY Notes: 1. Figure shows total number of ...
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CHARACTERISTICS t CES CE CLK t AVC AVD# t AVD t ACS Addresses Aa t ACH Data OE Hi-Z RDY Note: Figure assumes 6 wait states for initial ...
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CHARACTERISTICS Suspend CLK AVD# t OES Addresses t OE# CKZ Data D(20) RDY t RACC Note: Figure is for any even address other than 3Eh (or multiple thereof). Figure 18. Reduced Wait-state ...
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CHARACTERISTICS Suspend CLK AVD# t OES Addresses OE# t CKZ Data D(3E) RDY t RACC Figure 20. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh) Suspend CLK AVD# ...
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CHARACTERISTICS CLK AVD# A(n) Addresses OE# Data(1) t ACC RDY(1) Data(2) RDY(2) Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command ...
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CHARACTERISTICS CLK AVD# A(3D) Addresses OE# Data t ACC RDY Note: Figure assumes 6 wait states for initial access and synchronous read. The Set Configuration Register command sequence has ...
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CHARACTERISTICS CLK AVD# A(3E) Addresses(1) t OE# OES Data(1) t ACC RDY(1) (Even) Addresses(2) A(3F) Data(2) RDY(2) (Odd) Note: Figure assumes 6 wait states for initial access and synchronous ...
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CHARACTERISTICS Asynchronous Mode Read Parameter JEDEC Standard Description t Access Time from CE# Low CE t Asynchronous Access Time ACC t AVD# Low Time AVDP t Address Setup Time to Rising Edge ...
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CHARACTERISTICS CE# OE# WE# Data Addresses AVD# Note Read Address Read Data. Figure 28. Asynchronous Mode Read with Latched Addresses CE# OE# WE# Data Addresses AVD# Note: RA ...
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CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) t Ready to Read Mode ...
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CHARACTERISTICS Erase/Program Operations Parameter JEDEC Standard Description t t Write Cycle Time (Note 1) AVAV WC Address Setup t t AVWL AS Time (Notes 2, 3) Address Hold Time t t WLAX ...
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CHARACTERISTICS Program Command Sequence (last two cycles CLK AVDP AVD Addresses 555h Data A0h CE VCS ...
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CHARACTERISTICS Program Command Sequence (last two cycles CLK AVSW t AVHW AVD Addresses 555h Data A0h t DS CE#f OE ...
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CHARACTERISTICS Program Command Sequence (last two cycles) t AVCH CLK t ACS AVD# t AVDP Addresses 555h Data t CAS CE#f OE# t CSW t WP WE# t VCS ...
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CHARACTERISTICS Program Command Sequence (last two cycles) t AVCH CLK t AS AVD# t AVDP Addresses 555h Data t CAS CE#f OE# t CSW t WP WE# t VCS ...
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CHARACTERISTICS Erase Command Sequence (last two cycles CLK AVDP AVD Addresses 2AAh Data 55h CE VCS ...
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CHARACTERISTICS CE# AVD# WE# Addresses Data Don't Care OE# 1 µs V ACC Note: Use setup and hold times from conventional program operation. Figure 36. Accelerated ...
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CHARACTERISTICS AVD CE OE# t OEH WE# t ACC Addresses VA Data Notes: 1. Status reads in figure are shown as asynchronous Valid ...
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CHARACTERISTICS CE# CLK AVD# Addresses V A OE# t IACC Data RDY Notes: 1. The timings are similar to synchronous read timings Valid Address. Two read cycles are required ...
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CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time for ...
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CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect ...
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CHARACTERISTICS) Address boundary occurs every 64 words, beginning at address 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing. C60 C61 CLK 3C 3D Address (hex) (stays high) AVD# RDY(1) ...
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CHARACTERISTICS Address boundary occurs every 64 words, beginning at address 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing. C60 C61 CLK 3C 3D Address (hex) (stays high) AVD# RDY(1) ...
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CHARACTERISTICS Data AVD# OE# 1 CLK Wait State Decoding Addresses: A14, A13, A12 = “111” ⇒ Reserved A14, A13, A12 = “110” ⇒ Reserved A14, A13, A12 = “101” ⇒ 5 programmed, ...
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CHARACTERISTICS Last Cycle in Program or Sector Erase Command Sequence t WC CE# OE# WE# t WPH Data PD/30h Addresses PA/ AVD Note: Breakpoints ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter 32 Kword Sector Erase Time 4 Kword Chip Erase Time Word Programming Time Accelerated Word Programming Time Chip Programming Time (Note 3) Accelerated Chip Programming Time Notes: 1. ...
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PSRAM DC AND OPERATING CHARACTERISTICS Item Supply Voltage Supply Voltage for I/O Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply ...
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PSRAM AC CHARACTERISTICS Item Read Cycle Time Address Skew Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output ...
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PSRAM AC CHARACTERISTICS Address t SK Previous Data Valid Data Out Figure 47. Timing of Read Cycle (CE1 Address CE1#s CE2s OE# LB#, UB# t LBLZ, High-Z Data Out ...
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PSRAM AC CHARACTERISTICS Address t SK CE1 CE2s t SK LB#, UB# WE# High-Z Data In Data Out Figure 49. Timing Waveform of Write Cycle (WE# Control December 5, 2003 I ...
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PSRAM AC CHARACTERISTICS Address CE1#s LB#, UB# WE# Data In Data Out Figure 50. Timing Waveform of Write Cycle (CE1#s Control, CE2s = High ...
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PHYSICAL DIMENSIONS TLB089—89-ball Fine-Pitch Ball Grid Array (FBGA Package D 0.15 C (2X) INDEX MARK PIN A1 CORNER 10 TOP VIEW SIDE VIEW 6 b 89X ...
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REVISION SUMMARY Revision A (December 5, 2003) Initial release. Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, ...