S71AL016D SPANSION [SPANSION], S71AL016D Datasheet - Page 29

• Manufacturer Part Number: S71AL016D
• Description: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
• Manufacturer: SPANSION [SPANSION]

NOTE: See Table
August 4, 2004 S29AL016D_00_A1_E
Chip Erase Command Sequence
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle
must contain the data 90h; the second cycle the data 00h. Addresses are don’t
care for both cycles. The device then returns to reading array data.
Figure 3
gram Operations table in “AC Characteristics” for parameters, and to
for timing diagrams.
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table
for the chip erase command sequence.
9
for program command sequence.
illustrates the algorithm for the program operation. See the Erase/Pro-
A d v a n c e
Increment Address
Figure 3. Program Operation
Embedded
I n f o r m a t i o n
in progress
algorithm
Program
S29AL016D
9
shows the address and data requirements
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
No
Figure 17
29