AM49PDL127BH66IS SPANSION [SPANSION], AM49PDL127BH66IS Datasheet - Page 15
AM49PDL127BH66IS
Manufacturer Part Number
AM49PDL127BH66IS
Description
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2 M x 16-Bit) CMOS
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49PDL127BH66IS.pdf
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MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
December 16, 2003
A D V A N C E
Am49PDL127BH/Am49PDL129BH
I N F O R M A T I O N
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
13
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