EMC6D102_06 SMSC [SMSC Corporation], EMC6D102_06 Datasheet - Page 74

• Manufacturer Part Number: EMC6D102_06
• Description: Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
• Manufacturer: SMSC [SMSC Corporation]

Revision 0.4 (06-15-06)
7.2.40
Register
Address
90h
91h
92h
93h
Read/
Write
R/W
R/W
R/W
R/W
This register is an SMSC Test register.
Registers 90h-93h: TachX Option Registers
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Bit[0] SLOW
1= Force tach reading register to FFFFh if number of tach edges detected is greater than 0, but less
than programmed number of edges. (default)
0=Force tach reading register to FFFEh if number of tach edges detected is greater than 0, but less
than programmed number of edges.
Bit[2:1] The number of edges for tach1 reading:
00=2 edges
01=3 edges
10=5 edges (default)
11=9 edges
Bit[3] Tachometer Reading Mode
0=mode 1 – standard
1=mode 2 – enhanced. (default)
Bit[4] Tach (Mode 2 only)
0=Don’t ignore first 3 edges (default)
1=Ignore first 3 tachometer edges after guard time
Note: This bit has been added to support a small sampling of fans that emit irregular tach pulses
Bit[7:5] PWM max stretching time
000=disable stretching
001=50msec
010=100msec
011=200msec
100=400msec
101=600msec
110=800msec (default)
when the PWM transitions ‘ON’. Typically, the guard time is sufficient for most fans.
Register Name
Tach1 Option
Tach2 Option
Tach3 Option
Tach4 Option
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
STCH2
STCH2
STCH2
STCH2
(MSb)
Bit 7
DATASHEET
STCH1
STCH1
STCH1
STCH1
Bit 6
74
STCH0
STCH0
STCH0
STCH0
Bit 5
3EDG
3EDG
3EDG
3EDG
Bit 4
MODE
MODE
MODE
MODE
Bit 3
EDG1
EDG1
EDG1
EDG1
Bit 2
EDG0
EDG0
EDG0
EDG0
Bit 1
SMSC EMC6D102
SLOW
SLOW
SLOW
SLOW
(LSb)
Bit 0
Datasheet
Default
Value
CCh
CCh
CCh
CCh