EMC6D103_07 SMSC [SMSC Corporation], EMC6D103_07 Datasheet
EMC6D103_07
Related parts for EMC6D103_07
EMC6D103_07 Summary of contents
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PRODUCT FEATURES 3.3 Volt Operation (5 Volt Tolerant Input Buffers) SMBus 2.0 Compliant Interface (Fixed, not Discoverable) with Three Slave Address Options Fan Control — PWM (Pulse width Modulation) Outputs (3) — Fan Tachometer Inputs (4) — Programmable automatic fan ...
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ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Chapter 9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 2.1 EMC6D103 24 Pin SSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet List of Tables Table 3.1 Pin Description ...
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Table 8.40 Registers 6D-6Eh: Zone Hysteresis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Chapter 1 General Description The EMC6D103 is an environmental monitoring device with automatic fan control capability. This ACPI compliant device provides hardware monitoring for up to five ...
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Chapter 2 Pinout This Environmental Monitoring and Control device (EMC) is offered pin SSOP mechanical package. 2.1 EMC6D103 Pinout SDA 1 2 SCLK 3 VSS 4 VCC 5 VID0 6 VID1 7 VID2 8 VID3 9 TACH3/INT# ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Chapter 3 Pin Description 3.1 Pin Functions PIN # NAME 1 SDA System Management Bus bi-directional Data. Open Drain output. 2 SCLK System Management Bus Clock. 5 ...
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PIN # NAME 11 TACH1 Input for monitoring a fan tachometer input. 12 TACH2 Input for monitoring a fan tachometer input. 9 TACH3 Input for monitoring a fan tachometer input. /Interrupt output to indicate a thermal /INT# and/or voltage event. ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 3.3 3.3V Operation, 5V Tolerance The EMC6D103 is intended to operate with a nominal 3.3V power supply. The analog voltage pins are connected to voltage sources at ...
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Chapter 4 Operational Description 4.1 Maximum Guaranteed Ratings Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet PARAMETER SYMBOL Analog-to-Digital Converter Characteristics Total Unadjusted Error Differential Non-Linearity Power Supply Sensitivity Total Monitoring Cycle Time t (Cycle Mode, Default Averaging) Conversion Time (Continuous Mode, Default ...
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Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. Note 4.1 TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Chapter 5 SMBus Interface The host processor communicates with the Fan Monitoring device through a series of read/write registers via the SMBus interface. SMBus is a serial ...
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Start 0 1 SDA SCL Figure 5.1 Address Selection on EMC6D103 5.2 Slave Bus Interface The EMC6D103 device SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus device. The implementation in ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Write Byte The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol shown in Table 5.2 ...
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Slave Device Time-Out The EMC6D103 supports the slave device timeout as per the SMBus Specification, v2.0. According to SMBus specification, v2.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Note: The INT# signal is an alternate function on the PWM2 and TACH3 pins. The EMC6D103 device will respond to the SMBus Alert Response address even if ...
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Chapter 6 Hardware Monitoring The following sub-sections describe the EMC6D103 Hardware Monitoring features. 6.1 Input Monitoring The EMC6D103 device’s monitoring function is started by writing a ‘1’ to the START bit in the Ready/Lock/Start Register (0x40). Measured values from the ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet SFTR[7:5] REMOTE AVG2 AVG1 AVG0 DIODE Note: The default for the AVG[2:0] bits is ...
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Continuous Monitoring Mode In the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after the Start bit is set high. The time for each voltage and temperature reading is shown ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See the section titled Auto Fan Control Operating Mode on page ...
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Vccp_Error Vccp_Error_En (IER1[3]) VCC_Error VCC_Error_En (IER1[7]) 5V_Error 5V_Error_En (IER1[5]) Diode 1 Limit Diode 1_En (IER3[2]) Ambient Limit Ambient_En (IER3[1]) Diode 2 Limit Diode 2_En (IER3[3]) 12V_Error 12V_Error_En (IER1[6]) TACH1 Out-of-Limit TACH1_En (IER2[1]) TACH2 Out-of-Limit TACH2 _En (IER2[2]) ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet The occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the negative terminal is connected to ...
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The INT# pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2(Fan Tachs) register (80h) is used to enable this option. This pin will remain low while the associated fan error bit in the Interrupt Status ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet above VCC or below Ground, they are not diode protected to the power rails. The measured values are stored in the Reading registers and compared with the ...
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There are Remote Diode ( Fault status bits in Interrupt Status Register 2 (42h), which, when one, indicate a short or open-circuit on remote thermal diode inputs (Remote x+ and Remote x-). Before a remote diode conversion is ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 6.9.4 Offset Registers There are three offset registers: Offset Register Ambient (1Dh) Offset Register 2 (1Eh) Offset Register 1 (1Fh) Offset Register 1 is used for Remote ...
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Chapter 7 Fan Control The following sections describe the various fan control and monitoring modes in the part. 7.1 General Description This Fan Control device is capable of driving multiple DC fans via three PWM outputs and monitoring up to ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 1. Set limits and parameters (not necessarily in this order) a. [5F-61h] Set PWM frequencies and Auto Fan Control Range. b. [62-63h] Set Ramp Rate Control and ...
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When in manual mode, the current PWM duty cycle registers can be written to adjust the speed of the fans, when the start bit is set. These registers are not writable when the lock bit is set. Note: The PWMx ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet No End Fan Spin Up Yes Spin Up Time Elapsed? (5C-5E) Yes Override all PWM outputs to 100% Yes duty cycle except if disabled or in manual ...
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The speed of the fan is controlled by the duty cycle set for that device. The duty cycle for the minimum fan speed must be programmed in Registers 64h-66h: PWMx Minimum Duty Cycle. This value corresponds to the speed of ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet MIN/OFF bit = 0 (Fan off when temperature is below minimum) Temp Tmax =Tmin +Trange Tmin PWM Duty Spin-Up Cycle Time Max =FFh min Notes: 1. When ...
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PWM Output tach reading FFFFh vs. tach limit Note: When Spin Up Reduction is enabled (SUREN), the Spin Up time will be less than or equal to the programmed time for Spin Up. Once the tachometer(s) ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet cycle. If the current PWM duty cycle is equal to the calculated duty cycle the PWM output will remain unchanged. Internally, the PWM Ramp Rate Control Logic ...
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PWM RAMP TIME (SEC) (TIME FROM 33% RRX- DUTY CYCLE TO [2:0] 100% DUTY CYCLE) 100 4.4 101 3.0 110 1.6 111 0.8 Example 1: PWM period < Ramp Rate Step Size PWM frequency = 87.7Hz (11.4msec) & PWM Ramp ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 7.1.4 Fan Speed Monitoring The chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. The fan tachometer ...
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Tach Reading register will be set to either FFFEh or FFFFh depending on the state of the Slow Tach bits located in the TACHx Options registers at offsets 90h - 93h. Software can easily compute the RPM value ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet The Tachometer circuit begins monitoring the tach when the associated PWM output transitions high and the guard time has expired. Each tach circuit will continue monitoring until ...
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The Tachometer registers are read only – a write to these registers has no effect. Mode 1 should be enabled and the tachometer limit register should be set to FFFFh if a tachometer input is left unconnected. 7.1.4.6 Programming Options ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet -Mode 1: If the programmed number of edges occurs before the counter reaches FFFFh latch the tachometer count -Mode 2: If the programmed number of edges occurs ...
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Table 7.3 Minimum RPM Detectable Using 3 Edges – No PWM Stretching PWM PULSE WIDTH AT DUTY CYCLE FREQUENCY (PWM ”ON” TIME) 25% (HZ) (MSEC) (MSEC) 87.7 2.85 58.6 4.27 44 5.68 35.2 7.1 29.3 8.53 21.9 11.42 14.6 17.12 ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Table 7.5 Minimum RPM Detectable– With PWM Stretching NUMBER OF EDGES 50MSE FOR DETECTION C 9 2400 5 1200 3 600 2 300 Note: Minimum RPM values ...
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Inhibit fan tachometer interrupts when the associated PWM is ‘OFF’. See the description of the PWM_TACH register. The default configuration is: PWM1 -> TACH1. PWM2 -> TACH2. PWM3 -> TACH3 & TACH4. Revision 0.3 (03-01-07) Fan Control Device with ...
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Chapter 8 Register Set Definition for the Lock and Start columns: Yes = Register is made read-only when the related bit is set Register is not made read-only when the related bit is set. Reg Read Reg Name ...
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Reg Read Reg Name Addr /Write 3Eh R Company ID 3Fh R Version / Stepping 40h R/W Ready/Lock/Start Note 8.2 41h R-C Interrupt Status Register 1 Note 8.3 42h R-C Interrupt Status Register 2 Note 8.3 43h R VID0-4 44h ...
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Reg Read Reg Name Addr /Write 5Ch R/W PWM 1 Configuration 5Dh R/W PWM 2 Configuration 5Eh R/W PWM 3 Configuration 5Fh R/W Zone 1 Range/PWM 1 Frequency 60h R/W Zone 2 Range/PWM 2 Frequency 61h R/W Zone 3 Range/PWM ...
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Reg Read Reg Name Addr /Write 7Ch R/W Special Function Register Note 8.4 7Dh R Reserved 7Eh R/W Interrupt Enable 1 (Voltages) 7Fh R/W Configuration 80h R/W Interrupt Enable 2 (Fan Tachs) 81h R/W TACH_PWM Association 82h R/W Interrupt Enable ...
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Reg Read Reg Name Addr /Write 92h R/W Tach3 Option 93h R/W Tach4 Option 94h R/W PWM1 Option 95h R/W PWM2 Option 96h R/W PWM3 Option 97h R/W SMSC Test Register 98h R/W SMSC Test Register 99-FEh R Reserved FFh ...
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Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted results. Note 8.1 The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual mode. In this case, the register is ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Offset Register Ambient only ...
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Registers 25-27h: Temperature Reading Table 8.6 Registers 25-27h: Temperature Reading Register Read/ Register Name Address Write 25h R Remote Diode 1 Temp Reading 26h R Internal Temp Reading 27h R Remote Diode 2 Temp Reading The Temperature Reading registers ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 8.2.5 Registers 28-2Fh: Fan Tachometer Reading Table 8.8 Registers 28-2Fh: Fan Tachometer Reading Register Read/ Register Name Address Write 28h R Tach1 LSB 29h R Tach1 MSB ...
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The Current PWM Duty registers store the duty cycle that the chip is currently driving the PWM signals at. At initial power-on, the duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start Register ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 8.2.7 Register 3Eh: Company ID Register Read/ Register Name Address Write 3Eh R Company ID The Company ID register contains the company identification number. This number is ...
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BIT NAME R/W DEFAULT 0 START R LOCK R READY OVRID R/W 0 4-7 Reserved R 0 Note: There is a start-up time 82ms for monitoring after the start bit ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 8.2.10 Register 41h: Interrupt Status Register 1 Table 8.15 Register 41h: Interrupt Status Register 1 Register Read/ Register Name Address Write 41h R-C Interrupt Status 1 (See ...
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BIT NAME R/W DEFAULT 0 2.5V_Error Vccp_Error VCC_Error 5V_Error Remote R 0 Diode 1 Limit Error 5 Internal R 0 Sensor Limit Error 6 Remote R 0 Diode ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet The remote diode fault bits do not clear on a read while the fault condition exists. If the start bit is set when a fault condition occurs, ...
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Software uses the information in this register to determine the voltage that the processor is designed to operate at. With this information, software can then dynamically determine the correct values to place in the Vccp Low Limit and Vccp High ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 8.2.14 Registers 4E-53h: Temperature Limit Registers Table 8.22 Registers 4E-53h: Temperature Limit Registers Register Read/ Register Name Address Write 4Eh R/W Remote Diode 1 Low Temp 4Fh ...
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Registers 54-5Bh: Fan Tachometer Low Limit Table 8.24 Registers 54-5Bh: Fan Tachometer Low Limit Register Read/ Register Name Address Write 54h R/W Tach1 Minimum LSB 55h R/W Tach1 Minimum MSB 56h R/W Tach2 Minimum LSB 57h R/W Tach2 Minimum ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet When in manual control mode, the PWMx Current Duty Cycle Registers (30h-32h) become Read/Write then possible to control the PWM outputs with software by writing ...
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Registers 5F-61h: Zone Temperature Range, PWM Frequency Table 8.28 Registers 5F-61h: Zone Temperature Range, PWM Frequency Register Read/ Register Name Address Write 5Fh R/W Zone 1 Range / Fan 1 Frequency 60h R/W Zone 2 Range / Fan 2 ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Example for PWM1 assigned to Zone 1: Zone 1 Low Temp Limit (Register 67h) is set to 50 ° C (32h). Zone 1 Range (Register 5Fh) is ...
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Table 8.30 Register Setting vs. Temperature Range (continued) RAN[3:0] Note: The range numbers will be used to calculate the slope of the PWM ramp up. For the fractional entries, the PWM will go on full when the temp reaches the ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Ramp Rate Control The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time. This period of time ...
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MINIMUM PWM DUTY 25 50 100% 8.2.20 Registers 67-69h: Zone Low Temperature Limit Table 8.36 Registers 67-69h: Zone Low Temperature Limit Register Read/ Register Name Address Write 67h R/W Zone ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Table 8.37 Temperature Limit vs. Register Setting (continued) LIMIT 50 ° 127 ° c 8.2.21 Registers 6A-6Ch: Absolute Temperature Limit Table 8.38 egisters ...
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Table 8.39 Absolute Limit vs. Register Setting (continued) ABSOLUTE LIMIT 50 ° 127 ° c 8.2.22 Registers 6D-6Eh: Zone Hysteresis Registers Table 8.40 Registers 6D-6Eh: Zone Hysteresis Registers Register Read/ Register Name Address Write 6Dh R/W ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet The part incorporates an XOR tree test mode. When the test mode is enabled by setting the ‘XEN’ bit high via SMBus, the part enters XOR test ...
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Register 7Ch: Special Function Register Table 8.46 Register 7Ch: Special Function Register Register Read Register Name Address /Write 7Ch R/W Special Function This register becomes read only when the Lock bit is set. Any further attempts to write to ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Table 8.47 AVG[2:0] Bit Decoder (continued) SFTR[7:5] AVG2 AVG1 AVG0 REM DIODE Note: The default for the AVG[2:0] bits is ...
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Register 7Fh: Configuration Register Table 8.49 Register 7Fh: Configuration Register Register Read/ Register Name Address Write 7Fh R/W Configuration These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 0=Out-of-limit tachometer readings do not affect the state of the INT# pin (default) 1=Enable out-of-limit tachometer readings to make the INT# pin active low Bit[1] Fan Tach ...
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Bits[1:0], Bits[3:2], Bits[5:4], Bits[7: Notes: Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1. All TACH inputs must be associated with a PWM output. If the tach ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 8.2.33 Registers 85h-88h: A/D Converter LSbs Registers Table 8.54 Registers 85h-88h: A/D Converter LSbs Registers Register Read Register Address /Write Name 85h R A/D Converter LSbs Reg ...
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Registers 8Ch: SMSC Test Register Table 8.58 Registers 8Ch: SMSC Test Register Register Read/ Register Name Address Write 8Ch R SMSC Test Register 8.2.38 Registers 8Dh: SMSC Test Register Table 8.59 Registers 8Dh: SMSC Test Register Register Read/ Register ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Bit[2:1] The number of edges for tach1 reading: 00=2 edges 01=3 edges 10=5 edges (default) 11=9 edges Bit[3] Tachometer Reading Mode 0=mode 1 – standard 1=mode 2 ...
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Bit[2] Snap to Zero (SZEN) This bit determines if the PWM output ramps down to OFF immediately set to zero. 0=Step Down the PWMx output to Off at the programmed Ramp ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 8.2.44 Register FFh: SMSC Test Register Table 8.65 Register FFh: SMSC Test Register Register Read Register Address /Write Name 98h R SMSC Test Register This register is ...
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Chapter 9 Timing Diagrams 9.1 PWM Outputs The following section shows the timing for the PWM[1:3] outputs. FANx NAME DESCRIPTION t1 PWM Period (Note 9.1) t2 PWM High Time (Note Note 9.1 This value is programmable by the PWM frequency ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 9.2 SMBus Interface t LOW SCLK t t HD;STA HD;DAT SDA t BUF P S SYMBOL PARAMETER Fsmb SMB Operating Frequency Tsp Spike Suppression Tbuf Bus free ...
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Chapter 10 Mechanical Specifications Figure 10.1 24-Pin SSOP Package Outline, 0.150” Wide Body, 0.025” Pitch Table 10.1 24-Pin SSOP Package Parameters MIN NOMINAL A 0.053 ~ A1 0.004 ~ 0.337 ~ E 0.228 ~ E1 0.150 ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Appendix AADC Voltage Conversion Table A.1 Analog-to-Digital Voltage Conversions for Hardware Monitoring Block INPUT VOLTAGE <0.062 <0.026 0.062–0.125 0.026–0.052 0.125–0.188 0.052–0.078 ...
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Appendix BExample Fan Circuits The following figures show examples of circuitry on the board for the PWM outputs, tachometer inputs, and remote diodes. Figure B.1, "Fan Drive Circuitry (Apply to PWM Driving Two Fans)" shows how the part can be ...
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet PWMx Figure B.2 Fan Drive Circuitry (Apply to PWM Driving One Fan) Output from Fan Note: For fans controlled directly by a PWM suggested to ...
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Remote Diode + Remote Diode - Figure B.4 Remote Diode (Apply to Remote2 Lines) Notes: 1. 2.2nF cap is optional and should be placed close to the EMC6D103 if used. 2. The voltage at PWM3 must be at least 2.0V ...