MT4C4001JC-12/883C AUSTIN [Austin Semiconductor], MT4C4001JC-12/883C Datasheet

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MT4C4001JC-12/883C

Manufacturer Part Number
MT4C4001JC-12/883C
Description
1 MEG x 4 DRAM Fast Page Mode DRAM
Manufacturer
AUSTIN [Austin Semiconductor]
Datasheet
1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\
(CBR), and HIDDEN
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
• Timing
• Packages
*NOTE: If solder-dip and lead-attach is desired on LCC
packages, lead-attach must be done prior to the solder-
dip operation.
MT4C4001J
Rev. 2.2 06/05
Ceramic SOJ
Ceramic SOJ w/ Cu J-lead
Ceramic Gull Wing
Ceramic LCC*
Ceramic ZIP
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
70ns access
80ns access
100ns access
120ns access
For more products and information
www.austinsemiconductor.com
please visit our web site at
Austin Semiconductor, Inc.
MARKING
-7
-8
-10
-12
CN
C
ECN
CZ
ECJ
ECJA
ECG
No. 103
No. 104
No. 202
No. 400
No. 504
No. 504A
No. 600
1
GENERAL DESCRIPTION
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles each bit is
uniquely addressed through the 20 address bits which are
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the
first 10 bits and CAS\ the later 10 bits. A READ or WRITE
cycle is selected with the WE\ input. A logic HIGH on WE\
dictates READ mode while a logic LOW on WE\ dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE\ or CAS\, whichever occurs last. If
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)
remain open (High-Z) until the next CAS\ cycle. If WE\ goes
LOW after data reaches the output pin(s), Qs are activated and
retain the selected cell data as long as CAS\ remains low
(regardless of WE\ or RAS\). This LATE WE\ pulse results in
a READ-WRITE cycle. The four data inputs and four data
outputs are routed through four pins using common I/O and
pin direction is controlled by WE\ and OE\. FAST-PAGE-
MODE operations allow faster data operations (READ,
WRITE, or READ-MODIFY-WRITE) within a row address
(A0-A9) defined page boundary. The FAST PAGE MODE
RAS\
DQ1
DQ2
WE\
Vcc
A9
A0
A1
A2
A3
The MT4C4001J is a randomly accessed solid-state
20-Pin DIP (C, CN)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
2
3
4
5
6
7
8
9
10
RAS\ 9
DQ3 3
DQ2 7
Vcc 15
OE\ 1
Vss
A0 11
A2 13
A5 17
A7 19
20-Pin DIP (CZ)
20
19
18
17
16
15
14
13
12
11
PIN ASSIGNMENT
5
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4
2 CAS\
4 DQ4
6 DQ1
8 WE\
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
(Top View)
RAS\
DQ1
DQ2
WE\
Vcc
A9
A0
A1
A2
A3
20-Pin Gull Wing (ECG)
20-Pin LCC (ECN), &
MT4C4001J
2
3
4
5
9
10
11
12
13
(ECJ,ECJA),
20-Pin SOJ
1
DRAM
DRAM
DRAM
DRAM
DRAM
(continued)
26
25
24
23
22
18
17
16
15
14
Vss
DQ4
DQ3
CAS\
OE\
A8
A7
A6
A5
A4

Related parts for MT4C4001JC-12/883C

MT4C4001JC-12/883C Summary of contents

Page 1

... Austin Semiconductor, Inc. 1 MEG x 4 DRAM Fast Page Mode DRAM AVAILABLE AS MILITARY SPECIFICATIONS • SMD 5962-90847 • MIL-STD-883 FEATURES • Industry standard x4 pinout, timing, functions, and packages • High-performance, CMOS silicon-gate process • Single +5V±10% power supply • Low-power, 2.5mW standby; 300mW active, typical • ...

Page 2

... RAS\ addressing. FAST PAGE MODE *EARLY-WRITE DETECTION CIRCUIT 10 1024 10 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DRAM DRAM DRAM DRAM DRAM MT4C4001J 4 DATA IN DQ1 BUFFER DQ2 DQ3 DQ4 DATA OUT 4 BUFFER 4 OE\ ...

Page 3

... Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DRAM DRAM DRAM DRAM DRAM MT4C4001J ADDRESSES DATA IN/OUT DQ1-DQ4 X X High-Z L ROW COL Data Out ROW COL Data In ...

Page 4

... CC I CC3 = t (MIN CC4 = t (MIN CC5 (MIN CC6 = t (MIN)) RC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DRAM DRAM DRAM DRAM DRAM MT4C4001J MIN MAX UNITS 4.5 5.5 V 2 -0.5 0 µ µA 2.4 V 0.4 V MAX -7 ...

Page 5

... RRH CLZ OFF WCS Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DRAM DRAM DRAM DRAM DRAM MT4C4001J UNITS NOTES -10 -12 MIN MAX MIN MAX UNITS NOTES 190 220 ...

Page 6

... WTS ORD OEH Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DRAM DRAM DRAM DRAM DRAM MT4C4001J -10 -12 MIN MAX MIN MAX UNITS NOTES ...

Page 7

... RWD CWD and t are setup and hold specifications for the WTH and t in the CBR REFRESH cycle. WRP WRH and t met (OE\ HIGH during WRITE cycle) OD OEH DRAM DRAM DRAM (MAX) RAD . RWD (MIN) and AWD are not AWD OFF ...

Page 8

... Austin Semiconductor, Inc. MT4C4001J Rev. 2.2 06/05 READ CYCLE EARLY-WRITE CYCLE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 DRAM DRAM DRAM DRAM DRAM MT4C4001J ...

Page 9

... Austin Semiconductor, Inc. (LATE-WRITE and READ-MODIFY-WRITE CYCLES) FAST-PAGE-MODE READ CYCLE MT4C4001J Rev. 2.2 06/05 READ-WRITE CYCLE Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 DRAM DRAM DRAM DRAM DRAM MT4C4001J ...

Page 10

... Austin Semiconductor, Inc. FAST-PAGE-MODE EARLY-WRITE CYCLE FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES LATE-WRITE cycle FAST READ-MODIFY-WRITE cycle PRWC MT4C4001J Rev. 2.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 DRAM DRAM DRAM DRAM DRAM MT4C4001J ...

Page 11

... Austin Semiconductor, Inc. (ADDR = A0-A9; WE\ = Don’t Care) CAS\-BEFORE-RAS\ REFRESH CYCLE MT4C4001J Rev. 2.2 06/05 RAS\-ONLY REFRESH CYCLE (A0-A9, and OE\ = DON’T CARE) HIDDEN REFRESH CYCLE (WE\ = HIGH, OE\ = LOW) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 DRAM DRAM DRAM DRAM DRAM MT4C4001J 24 ...

Page 12

... Austin Semiconductor, Inc. 4 MEG POWER-UP AND REFRESH CONSTRAINTS The EIA/JEDEC 4 Meg DRAM introduces two potential incompatibilities compared to the previous generation 1 Meg DRAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and providing for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg ...

Page 13

... BSC 0.100 BSC 0.015 0.125 0.005 90° Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 DRAM DRAM DRAM DRAM DRAM MT4C4001J MAX 0.200 0.026 0.065 0.018 1.060 0.310 0.070 0.200 --- ...

Page 14

... BSC 0.015 0.125 --- Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 DRAM DRAM DRAM DRAM DRAM MT4C4001J MAX 0.175 0.021 0.065 0.014 1.030 0.910 0.410 0.420 0.060 0.200 ...

Page 15

... SMD SPECIFICATIONS MIN MAX 0.355 0.405 0.016 0.023 0.035 0.045 0.008 0.015 0.045 0.055 0.085 0.115 1.035 1.065 0.100 0.130 0.125 0.200 0.015 0.050 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 DRAM DRAM DRAM DRAM DRAM MT4C4001J ...

Page 16

... TYP 0.022 0.343 0.665 0.590 0.050 TYP 0.045 0.080 0.006 0.025 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 DRAM DRAM DRAM DRAM DRAM MT4C4001J MAX 0.080 0.028 0.357 0.685 0.610 0.055 0.100 0.010 ...

Page 17

... ASI SPECIFICATIONS MIN 0.12 0.035 TYP 0.012 DIA 0.050 TYP 0.09 0.665 0.592 0.345 0.300 0.045 0.055 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 DRAM DRAM DRAM DRAM DRAM MT4C4001J MAX 0.14 0.016 DIA 0.110 0.685 0.608 0.355 0.315 0.055 0.065 ...

Page 18

... ASI SPECIFICATIONS MIN 0.12 0.035 TYP 0.012 DIA 0.016 DIA 0.050 TYP 0.09 0.665 0.592 0.345 0.300 0.045 0.055 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 DRAM DRAM DRAM DRAM DRAM MT4C4001J MAX 0.14 0.110 0.685 0.608 0.355 0.315 0.055 0.065 ...

Page 19

... TYP 0.090 0.665 0.592 0.345 0.482 0.442 0.045 0.014 Dia. TYP 0.057 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 DRAM DRAM DRAM DRAM DRAM MT4C4001J MAX 0.140 0.078 0.028 0.110 0.685 0.608 0.355 0.498 0.458 0.055 0.063 ...

Page 20

... Device Package Speed ns Number Type MT4C4001J ECJA MT4C4001J ECJA MT4C4001J ECJA MT4C4001J ECJA *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing MT4C4001J Rev. 2.2 06/05 EXAMPLE: MT4C4001JC-12/883C Device Process Number -7 /* MT4C4001J -8 /* MT4C4001J -10 /* MT4C4001J -12 /* MT4C4001J EXAMPLE: MT4C4001JECN-10/XT Device Process ...

Page 21

... ASI Package Designator C SMD Part # ASI Part # 5962-9084703MNA MT4C4001JC-8/883C 5962-9084702MNA MT4C4001JC-10/883C 5962-9084701MNA MT4C4001JC-12/883C ASI Package Designator ECN SMD Part # ASI Part # MT4C4001JECN-8/883C MT4C4001JECN-10/883C MT4C4001JECN-12/883C Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

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