MT4C4001JC-12/883C AUSTIN [Austin Semiconductor], MT4C4001JC-12/883C Datasheet - Page 7

• Manufacturer Part Number: MT4C4001JC-12/883C
• Description: 1 MEG x 4 DRAM Fast Page Mode DRAM
• Manufacturer: AUSTIN [Austin Semiconductor]

NOTES:
1. All voltages referenced to Vss.
2. This parameter is sampled, not 100% tested. Capacitance
is measured with Vcc=5V, f=1 MHz at less than 50mVrms,
T
output individually with remaining inputs and outputs open.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time and
the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate cycle
time at which proper operation over the full temperature range
(-55°C < T
7. An initial pause of 100µs is required after power-up
followed by eight RAS\ refresh cycles (RAS\-ONLY or CBR
with WE\ HIGH) before proper device operation is assured.
The eight RAS\ cycle wake-up should be repeated any time
the 16ms refresh requirement is exceeded.
8. AC characteristics assume t
9. V
measuring timing of input signals. Transition times are
measured between V
10. In addition to meeting the transition rate specification, all
input signals must transit between V
V
11. If CAS\ = V
12. If CAS\ = V
the last valid READ cycle.
13. Measured with a load equivalent to two TTL gates and
100pF.
14. Assumes that t
the maximum recommended value shown in this table, t
will increase by the amount that t
15. Assumes that t
16. If CAS\ is LOW at the falling edge of RAS\, DQs will be
maintained from the previous cycle. To initiate a new cycle
and clear the data out buffer, CAS\ must be pulsed HIGH for
t
17. Operation within the t
(MAX) can be met. t
point only; if t
limit, then access time is controlled exclusively by t
18. Operation within the t
(MAX) can be met. t
MT4C4001J
Rev. 2.2 06/05
CPN
A
IL
= 25°C ±3°C, Vbias = 2.4V applied to each input and
and V
.
IH
(MIN) and V
IH
A
) in a monotonic manner.
< 125°C) is assured.
RCD
IH
IL
, data outputs (DQs) are High-Z.
, data outputs (DQs) may contain data from
RCD
RCD
is greater than the specified t
IH
RCD
RAD
IL
< t
> t
and V
RCD
(MAX) are reference levels for
RCD
RCD
RAD
(MAX) is specified as a reference
(MAX) is specified as a reference
IL
Austin Semiconductor, Inc.
(MAX). If t
(MAX)
(MAX) limit ensures that t
(MAX) limit ensures that t
(or between V
T
RCD
= 5ns.
exceeds the value shown.
IH
and V
RCD
IL
IL
is greater than
and V
(or between
RCD
CAC
IH
(MAX)
).
.
RAC
RAC
RCD
7
point only; if t
limit, then access time is controlled exclusively by t
19. Either t
20. t
the open circuit conditions and is not referenced to V
V
21. t
parameters. t
t
If t
and the data output will remain an open circuit throughout the
entire cycle. If t
t
and the data output will contain data read from the selected
cell. If neither of the above conditions is met, the state of the
data out is indeterminate. OE\ held HIGH and WE\ taken LOW
after CAS\ goes LOW results in a LATE-WRITE (OE\
controlled) cycle. t
applicable in a LATE-WRITE cycle.
22. These parameters are referenced to CAS\ leading edge in
EARLY-WRITE cycle and WE\ leading edge in LATE-WRITE
cycles and WE\ leading edge in LATE-WRITE or
READ-MODIFY-WRITE cycle.
23. If OE\ is tied permanently LOW, LATE-WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE\=LOW and OE\=HIGH.
25. t
WE\ pin being held LOW to enable the JEDEC test mode (with
CBR timing constraints). These two parameters are the
inverts of t
26. LATE-WRITE and READ-MODIFY-WRITE cycles must
have both t
in order to ensure that the output buffers will be open during
the WRITE cycle. The DQs will provide the previously read
data if CAS\ remains LOW and OE\ is taken back LOW after
t
the DQs will remain open.
27. The DQs open during READ cycles once t
occur. If CAS\ goes HIGH first, OE\ becomes a “don’t care.”
If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t
care;” and the DQs will provide the previously read data if
OE\ is taken back LOW (while CAS\ remains LOW).
28. JEDEC test mode only.
CWD
OEH
AWD
OL
WCS
.
OFF
WCS
WTS
is met. If CAS\ goes HIGH prior to OE\ going back LOW,
, and t
> t
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
> t
(MAX) defines the time at which the output achieves
CWD
, t
and t
WCS
RWD
WRP
OD
RCH
CWD
(MIN), the cycle is a READ-MODIFY-WRITE
and t
WCS
WTH
, t
(MIN), the cycle is an EARLY-WRITE cycles
RAD
and t
or t
AWD
apply to READ-MODIFY-WRITE cycles.
RWD
applies to EARLY-WRITE cycles. t
OEH
RRH
is greater than the specified t
are setup and hold specifications for the
WRH
, and t
> t
WCS
met (OE\ HIGH during WRITE cycle)
must be satisfied for a READ cycle.
RWD
in the CBR REFRESH cycle.
, t
CWD
(MIN), t
RWD
are not restrictive operating
, t
CWD
MT4C4001J
AWD
, and t
> t
DRAM
DRAM
DRAM
DRAM
DRAM
AWD
AWD
RAD
(MIN) and
OD
AA
are not
(MAX)
or t
.
OH
RWD
OFF
or
,