WJCE6353SL9G5882170 INTEL [Intel Corporation], WJCE6353SL9G5882170 Datasheet
WJCE6353SL9G5882170
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WJCE6353SL9G5882170 Summary of contents
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Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV) Data Sheet Features • Compliant with ETSI 300 744 DVB-T, Unified Nordig and DTG performance specifications • High performance with fast fully blind acquisition and tracking capability ...
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Applications • Digital terrestrial set-top boxes • Integrated digital televisions • Personal video recorders • PC-TV receivers • Portable applications Description The CE6353 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds, with margin, the ...
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Pin & Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Pin Names - numeric ...
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Pin & Package Details 1.1 Pin Outline CE6353 Figure 2 - Pin Outline 6 Intel Corporation Data Sheet ...
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Pin Allocation Pin Function Pin 1 Vss 17 SADD1 2 Vdd 18 SADD0 3 Vss 19 CVdd 4 CLK1 20 Vss 5 DATA1 21 PLLVdd 6 IRQ 22 PLLGND 7 CVdd 23 XTI 8 Vss 24 XTO 9 RESET ...
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CVdd 59 MOSTRT CVdd 64 MOVAL DATA1 5 OSCMODE DATA2/GPP1 36 PLLGND Table 2 - Pin Names - alphabetical order (continued) 1.3 Pin Description Pin Description Table Pin No Name MPEG pins 47 MOSTRT 48 MOVAL 49-53, 56-58 MDO(0:4)/MDO(5:7) 61 ...
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Pin Description Table (continued) Pin No Name Analog inputs 30 VIN 31 VIN 34 RFLEV Supply pins 21 PLLVdd 22 PLLGnd 7, 19, 37, 39, 59, 64 CVdd 2, 13, 45, 54, Vdd 14, 20, 25, Vss ...
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Functional Description A functional block diagram of the CE6353 OFDM demodulator is shown in Figure 3. This accepts an IF analog signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and ...
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The FSM controller shown in Figure 3 controls both the demodulator and the FEC. It also drives the 2-wire bus to the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the received ...
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The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking. The AGC is free running during OFDM channel changes and locks to the new channel while the tuner ...
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Common Phase Error Correction This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the tuner phase noise on system performance. 2.10 Channel Equalization This consists of two parts. ...
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Viterbi Decoder The Viterbi decoder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit-stream. The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the ...
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Interfaces 3.1 2-Wire Bus 3.1.1 Host The primary 2-wire bus serial interface uses pins: • DATA1 (pin 5) serial data, the most significant bit is sent first. • CLK1 (pin 4) serial clock. The 2-wire bus address is determined ...
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Examples of 2-Wire Bus Messages KEY Italics Write operation - as a slave receiver: S DEVICE W A RADD ADDRESS (n) Read operation - CE6353 as a slave transmitter: S DEVICE R A DATA ADDRESS (reg ...
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Parameter CLK clock frequency (Primary) Bus free time between a STOP and START condition. Hold time (repeated) START condition. LOW period of CLK clock. HIGH period of CLK clock. Set-up time for a repeated START condition. Data hold time (when ...
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MPEG 3.2.1 Data Output Header Format Transport Packet Header 0 TEI MDO[7] Figure 6 - DVB Transport Packet Header Byte After decoding the 188-byte MPEG packet output on the MDO pins in 188 consecutive clock cycles. Additionally ...
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MPEG Data Output Signals The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be ...
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MOCLKINV 1 = Delay conditions Parameter Maximum Data output delay t 3.0 D Setup Time t 7.0 SU Hold Time t 7.0 H MOCLK MDO } MOSTRT MOVAL BKERRB BKERR 3.2.5 MOCLKINV 0 = MDOSWAP = 0 Parameter Maximum ...
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Electrical Characteristics 4.1 Recommended Operating Conditions Parameter Power supply voltage: Power supply current: 3 Input clock frequency CLK1 primary serial clock frequency Ambient operating temperature 1. Current from the 3.3 V supply will be mainly dependent on the external ...
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DC Electrical Characteristics DC Electrical Characteristics Parameter Conditions Operating periphery voltage core 1 Supply current 1.62>CVDD>1.98 Supply current sleep mode Outputs Output levels IOH 2mA 3.0>VDD>3.6 IOL 2mA 3.0>VDD>3.6 IOL 6mA 3.0>VDD>3.6 Output capacitance Not including track MDO(7:0), MOVAL, ...
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Selection of External Components The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is greater than unity. Correct selection of the two capacitors is very important and the following method ...
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Calculating Crystal Power Dissipation To calculate the power dissipated in a crystal the following equation can be used Equation 8 power dissipated in crystal at resonant frequency (W) ...
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Oscillator/Clock Application Notes • On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. Other signal tracks must not be allowed to cross through this area. The component tracks should ...
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Application Circuit CE6353 Figure 12 - Typical Application Circuit 26 Intel Corporation Data Sheet ...