WJCE6353SL9G5882170 INTEL [Intel Corporation], WJCE6353SL9G5882170 Datasheet - Page 15

• Manufacturer Part Number: WJCE6353SL9G5882170
• Description: Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV)
• Manufacturer: INTEL [Intel Corporation]

3.0
3.1
3.1.1
The primary 2-wire bus serial interface uses pins:
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•
The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.
In TNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:
When the CE6353 is powered up, the RESET pin 9 should be held low for at least 50 ms after VDD has reached
normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus
address. ADDR[0] is the R/W bit.
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive
mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD
register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following
byte. Not all addresses are valid and many are reserved registers that must not be changed from their default
values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access
the reserved registers accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address
is not recognized, the CE6353 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could next be followed with a write command to continue from the latest address. RADD would not be sent in this
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.
3.1.2
The CE6353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. See register
GPP_CTL address 0x8C.
Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.
The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.
ADDR[7]
VSS
DATA1 (pin 5) serial data, the most significant bit is sent first.
CLK1 (pin 4) serial clock.
2-Wire Bus
Interfaces
Host
Tuner
ADDR[6]
VSS
Not programmable
ADDR[5]
VSS
ADDR[4]
VDD
ADDR[3]
VDD
Intel Corporation
CE6353
15
ADDR[2]
SADD[1]
VDD
ADDR[1]
SADD[0]
VDD
Data Sheet