WJCE6353SL9G5882170 INTEL [Intel Corporation], WJCE6353SL9G5882170 Datasheet - Page 11

• Manufacturer Part Number: WJCE6353SL9G5882170
• Description: Nordig Unified DVB-T COFDM Terrestrial Demodulator for PC-TV and Hand-held Digital TV (DTV)
• Manufacturer: INTEL [Intel Corporation]

The FSM controller shown in Figure 3 controls both the demodulator and the FEC. It also drives the 2-wire bus to
the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the
received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This
mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software
overhead in the host driver.
The algorithms and architectures used in the CE6353 have been optimized to minimize power consumption.
2.1
The CE6353 has a high performance 10-bit analog-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz
bandwidth OFDM signal, with its spectrum centred at:
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An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highly
programmable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.
2.2
An AGC module compares the absolute value of the digitized signal with a programmable reference. The error
signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which
has to be RC low-pass filtered to obtain the voltage to control the amplifier.
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC
clipping and a small value results in excessive quantization noise. Hence the optimum value has been determined
assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit
theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This
reference or target value may have to be lowered slightly for some applications. Slope control bits have been
provided for the AGCs and these have to be set correctly depending on the gain-versus-voltage slope of the gain
control amplifiers.
36.17 MHz IF
43.75 MHz IF
5 - 10 MHz near-zero IF
Analog-to-Digital Converter
Automatic Gain Control
Figure 4 - FEC Block Diagram
Intel Corporation
CE6353
11
Data Sheet