H5PS5162FFR-S5 HYNIX [Hynix Semiconductor], H5PS5162FFR-S5 Datasheet - Page 7
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H5PS5162FFR-S5
Manufacturer Part Number
H5PS5162FFR-S5
Description
512Mb DDR2 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.H5PS5162FFR-S5.pdf
(39 pages)
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Rev. 1.0 / July. 2008
UDQS, UDQS
LDQS, LDQS
VSSDL
VDDQ
VDDL
VSSQ
VREF
VDD
PIN
VSS
NC
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input/
TYPE
Data Strobe : Output with read data, input with write data. Edge aligned with read data,
centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS
corresponds to the data on DQ8~DQ15. The data strobes DQS, LDQS and UDQS may be
used in single ended mode or paired with optional complementary signals DQS, LDQS
and UDQS to provide differential pair signaling to the system during both reads and
wirtes. An EMRS(1) control bit enables or disables all complementary data strobe sig-
nals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0
of EMRS(1)
of EMRS(1)
No Connect : No internal electrical connection is present.
DQ Power Supply: 1.8V +/- 0.1V
DQ Ground
DLL Power Supply : 1.8V +/- 0.1V
DLL Ground
Power Supply : 1.8V +/- 0.1V
Ground
Reference voltage for inputs for SSTL interface.
"single-ended DQS signals" refers to any of the following with A10 = 1
x16 LDQS/LDQS and UDQS/UDQS
x16 LDQS and UDQS
DESCRIPTION
H5PS5162FFR series
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Release
7