H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 15

• Manufacturer Part Number: H5TQ4G43AMR
• Description: 4Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.0 / Dec. 2009
(optional)
I
Symbol
I
I
I
DDQ2NT
I
I
I
DD2NT
DD2P0
DD2P1
DD2N
DD2Q
DD3N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
at 0; Pattern Details: see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
gling according to Table 6; Pattern Details: see Table 6.
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers
Mode: Slow Exit
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers
Mode: Fast Exit
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
at 0; Pattern Details: see Table 5.
c)
c)
Description
b)
b)
b)
; ODT Signal: stable at 0; Precharge Power Down
; ODT Signal: stable at 0; Precharge Power Down
; ODT Signal: stable at 0
a)
a)
a)
a)
a)
a)
; AL: 0; CS: stable at 1; Command, Address,
; AL: 0; CS: stable at 1; Command, Address,
; AL: 0; CS: stable at 1; Command, Address,
; AL: 0; CS: stable at 1; Command, Address,
; AL: 0; CS: stable at 1; Command, Address,
; AL: 0; CS: stable at 1; Command, Address,
b)
b)
b)
; ODT Signal: stable
; ODT Signal: stable
; ODT Signal: tog-
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