H5TQ4G43AMR HYNIX [Hynix Semiconductor], H5TQ4G43AMR Datasheet - Page 26

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H5TQ4G43AMR

Manufacturer Part Number
H5TQ4G43AMR
Description
4Gb DDR3 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
For specific Notes See “Speed Bin Table Notes” on page 29.
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
Rev. 1.0 / Dec. 2009
ACT to internal read or write delay time
ACT to ACT or REF command period
Internal read command to first data
CL = 5
CL = 6
ACT to PRE command period
PRE command period
Supported CWL Settings
Supported CL Settings
Parameter
CL - nRCD - nRP
Speed Bin
CWL = 5
CWL = 5
Symbol
t
t
CK(AVG)
CK(AVG)
t
t
RCD
t
t
t
RAS
AA
RP
RC
52.5
37.5
min
2.5
15
15
15
DDR3-800E
Reserved
6-6-6
6
5
9 * tREFI
max
3.3
20
Unit
n
n
ns
ns
ns
ns
ns
ns
ns
CK
CK
1, 2, 3, 4
Notes
1, 2, 3
26

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