LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 23

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

8.5.6 Processing during error recovery
• When the preambles B, M, and W are detected, the PLL circuit goes to the locked state and data demodulation starts.
• The DATAO output data is output on the first LRCK edge after ERROR goes low.
8.6 Channel Status Data Output
8.6.1 Data delimiter bit 1 output (
•
8.6.2 Emphasis information output (E/INT)
• E/INT is shared by the microcontroller interface interrupt function. However, in the initial state, it outputs the
______________
AUDIO outputs channel status bit 1, which indicates whether or not the input bi-phase data is PCM audio data.
presence or absence of emphasis with a time constant of 50/15µs for use in consumer products or broadcast studios.
______
AUDIO pin
E/INT pin
Internal clock signal
High
High
Low
Low
ERROR
DATAO
LRCK
Output starts at the LRCK edge immediately following the fall of the ERROR flag.
Figure 8.11 Data Processing when Data Demodulation Starts
______________
AUDIO )
Table 8.10
Table 8.11 E/INT Output
OK
LC89052TA-E
______________
AUDIO Output
PCM audio data (CS bit 1 = low)
15 ms to 50 ms
Non-PCM data (CS bit 1 = high)
50/15µs pre-emphasis
Output conditions
Output conditions
No pre-emphasis
data
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