YMF724 ETC, YMF724 Datasheet - Page 21

• Manufacturer Part Number: YMF724
• Description: high performance audio controller for the PCI Bus
• Manufacturer: ETC

YMF724F
46-47h: Subsystem ID Write Register
48-49h: DS-1 Control Register
4A-4Bh: DS-1 Power Control Register
b[15:0] ........Subsystem ID Write Register
b0................CRST: AC’97 Software Reset Signal Control
b1................XRST: Local Device Software Reset Signal Control
b0................DMC: Disable Master Clock Oscillation
b1................DPLL0: Disable PLL0 Clock Oscillation
PR7
This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register).
The default value is the DS-1 Device ID, 000Dh. IHVs must change this ID to their ID in the BIOS
POST routine.
In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID.
This bit controls the CRST# signal.
This bit controls the XRST# signal.
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
Setting this bit to “1” disables the oscillation of PLL for the Legacy Audio function.
b15
b15
b15
“0”: Inactive (CRST#=High)
“1”: Active (CRST#=Low)
“0”: Inactive (XRST#=High)
“1”: Active (XRST#=Low)
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
-
Read / Write
Default: 000Dh
Access Bus Width: 16-bit
Read / Write
Default: 0001h
Access Bus Width: 8, 16, 32-bit
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
PR6
b14
b14
b14
-
PR5
b13
b13
b13
-
PR4
b12
b12
b12
-
(default)
(default)
PR3
b11
b11
b11
-
PR2
(default)
b10
b10
(default)
b10
-
PR1
b9
b9
b9
-
Subsystem ID Write
-21-
PR0
b8
b8
b8
-
b7
b7
b7
-
-
b6
b6
b6
-
-
PSN
b5
b5
b5
-
PSL1
b4
b4
b4
-
PSL0 DPLL1 DPLL0 DMC
b3
b3
b3
-
January 14, 1999
b2
b2
b2
-
XRST CRST
b1
b1
b1
b0
b0
b0