AN10436 PHILIPS [NXP Semiconductors], AN10436 Datasheet - Page 18

• Manufacturer Part Number: AN10436
• Description: TDA8932B/33(B) Class-D audio amplifier
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
Table 3.
AN10436_1
Application note
Symbol
V
IN1P
IN1N
DIAG
ENGAGE
POWERUP
CGND
V
V
OSCREF
HVPREF
INREF
TEST
IN2N
IN2P
DREF
SSD(HW)
DDA
SSA
Pin description
Pin
1, 16,
17, 32
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
2.8 Pin description
Fig 9. Pin configuration HTSSOP32
Description
Negative digital supply voltage and handle wafer connection (heat spreader). With an
asymmetrical supply, the V
the V
Positive audio input for power stage 1.
Negative audio input for power stage1.
Input/output to indicate the FAULT mode. DIAG has an internal pull-up and should left floating
when unused.
Input with internal pull-up to switch between MUTE mode and OPERATING mode.
Input to switch between SLEEP mode and MUTE mode.
Control ground, reference for POWERUP, ENGAGE and DIAG. This CGND is connected to the
supply ground.
Positive analog supply voltage.
Negative analog supply voltage.
Input to set the frequency for the internal oscillator (master configuration). In slave configuration
this pin should be connected to V
Decoupling of the internal half supply voltage reference (asymmetrical supply). With a
symmetrical supply, this pin should be connected to the CGND (supply ground).
Decoupling for the input reference voltage.
Test signal input for testing purpose only (leave floating or connect to V
Negative audio input for power stage 2.
Positive audio input for power stage 2.
Decoupling of the internal 5 V regulator.
SSD(HW)
is connected to the negative supply line, V
POWERUP
Rev. 01 — 12 December 2007
V
V
ENGAGE
OSCREF
HVPREF
SSD(HW)
SSD(HW)
CGND
INREF
TEST
DIAG
V
V
IN1N
IN2N
IN1P
IN2P
SSD(HW)
DDA
SSA
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
SSA
is connected to the supply ground. With a symmetrical supply,
.
TDA8932BTW
TDA8933BTW
TDA8932B/33(B) Class-D audio amplifier
010aaa423
SSA
.
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
OSCIO
HVP1
V
BOOT1
OUT1
V
STAB1
STAB2
V
OUT2
BOOT2
V
HVP2
DREF
V
SSD(HW)
DDP1
SSP1
SSP2
DDP2
SSD(HW)
SSA
).
AN10436
© NXP B.V. 2007. All rights reserved.
18 of 55