DM9010_06 DAVICOM [Davicom Semiconductor, Inc.], DM9010_06 Datasheet - Page 24

• Manufacturer Part Number: DM9010_06
• Description: 10/100 Mbps Single Chip Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.26 Operation Test Control Register ( 2EH )
6.27 Special Mode Control Register ( 2FH )
6.28 Early Transmit Control/Status Register ( 30H )
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
3~0
7~6
2~0
6~3
4~2
Bit
Bit
Bit
4
5
4
3
7
2
1
0
7
6
5
RESERVED
RESERVED
ONEPM
PHYOP
SM_EN
EXTMII
Name
Name
Name
ETS2
ETS1
IFGS
SCC
SOE
SCS
ETE
FLC
FB1
FB0
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RO
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
HPS0, RW
HPS0,RO
HPS0,RO
Default
Default
000,RO
Default
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11:1KHz
In external MII mode, only internal system clock is always 50Mhz.
Force to External MII mode
SRAM Output-Enable Always ON
SRAM Chip-Select Always ON
PHY operation mode
Special Mode Enable
Reserved
Force Late Collision
Force Longest Back-off time
Force Shortest Back-off time
Early Transmit Enable
Enable bits[1:0]
Early Transmit Status II (underrun)
Early Transmit Status I (underrun)
Reserved
Single Chip Ethernet Controller with General Processor Interface
Description
Description
Description
DM9010
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