AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 13
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AX88796BLI
Manufacturer Part Number
AX88796BLI
Description
Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.AX88796BLI.pdf
(82 pages)
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4.1.3 Broadcast Address Match Filter
4.1.4 VLAN Match Filter
Layer 2
If address Y is found to hash to the value 32 (20H), then FB32 (ref. 4.1.2) in MAR2 should be initialized to ``1''. This
will cause the AX88796B to accept any multicast packet with the address Y.
Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to
64 logical address filters if these addresses are chosen to map into unique locations in the multicast filter.
Note:
The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s,
which is the values are “FF FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the
Protocol Control Logic rejects the packet.
AX88796B compares the thirteenth and fourteenth bytes of receive frames. If not match with VLAN_ID1,
VLAN_ID_0 (offset 1dh, 1ch) then reject current frame. The VLAN filter will always accept VLAN_ID is zero of
receive frames due to it is 802.1q (for priority purpose) frames. The maximum length of the good packet is thus
change from 1518 bytes to 1522 bytes.
Frame (64-1518 Bytes)
VLAN (64-1522 Bytes)
The first bit of received packet sequence is 1’s stands by Multicast Address.
Latch
1 of 64-bit decoder
Filter bit array
32-bit CRC Generator
7 Bytes
Preamble
X=31 to X=26
1 Byte
SFD
Destination
Clock
Address
6 Bytes
Address
6 Bytes
Source
Selected bit
0 = reject, 1= accept
VLAN tagging
8100
2 B
802.1Q
2 B
13
TCI
Priority
3 bits
2 B
L/T
AX88796BLF / AX88796BLI
1 bit
CFI
ASIX ELECTRONICS CORPORATION
VLAN ID
12 bits
46-1500 Bytes
Data
Pad
4 Bytes
FCS
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