AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 40
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AX88796BLI
Manufacturer Part Number
AX88796BLI
Description
Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.AX88796BLI.pdf
(82 pages)
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5.1.20 Transmit Configuration Register (TCR)
Page0 Offset 0DH (Write)
5.1.21 Frame Alignment Error Tally Register (CNTR0)
Page0 Offset 0DH (Read)
5.1.22 Data Configuration Register (DCR)
Page0 Offset 0EH (Write)
5.1.23 CRC Error Tally Register (CNTR1)
Page0 Offset 0EH (Read)
Field
7
6
5
4:3
2:1
0
Field
7:0
Field
7:2
1
0
Field
7:0
PD
-
LB1, LB0 Encoded Loop-back Control
CNTR0
-
WTS
CNTR1
Name
FDU
RLO
CRC
Name
Name
-
Name
Description
Full Duplex
This duplex setting was wire or with MCR bit-7. Each one goes high then configures MAC
as full-duplex. AX88796B will ignore this bit and MCR bit-7 when using internal PHY.
Pad Disable
Retry of late collision
Reserved
Mode0
Mode 1
Mode 2
No Define 1
Inhibit CRC
Description (Default = 00h)
This counter is incremented every time a packet is received with a Frame Alignment Error.
The packet must have been recognized by the address recognition logic. The counter is
cleared after the processor reads it.
Description
Reserved
Reserved
Word Transfer Select (Data Port Only)
Description (Default = 00h)
This counter is incremented every time a packet is received with a CRC error. The packet
must first be recognized by the address recognition logic. The counter is cleared after the
processor reads it.
This bit configure MAC media mode is Full Duplex or not.
0: Pad will be added when packet length less than 60. (Default)
1: Pad will not be added when packet length less than 60.
0: Don’t retransmit packet when late collision happens. (Default)
1: Retransmit packet when late collision happens.
These encoded configuration bits set the type of loop-back that is to be performed.
0: CRC appended by transmitter. (Default)
1: CRC inhibited by transmitter.
0: Selects Data Port with byte-wide transfers. (Default)
1: Selects Data Port with word-wide transfers.
0: Half duplex (Default)
1: Full duplex
LB1 LB0
0
0
1
0
1
0
1
Normal operation (Default)
Internal AX88796B loop-back
PHY loop-back
Reserved
40
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION