AX88796BLI ASIX [ASIX Electronics Corporation], AX88796BLI Datasheet - Page 30
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AX88796BLI
Manufacturer Part Number
AX88796BLI
Description
Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.AX88796BLI.pdf
(82 pages)
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5.0 Registers Operation
5.1 MAC Control and Status Registers (CSR)
All registers of MAC Core are 8-bit wide except data port (DP). Data Port is optional 8 or 16-bit wide by WTS
(DCR). Offset 01h to 0Fh mapped into pages, which are selected by PS (Page Select) in the Command Register.
10H, 11H
Offset
0AH
0BH
0CH
0DH
1AH
1BH
1CH
1DH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0EH
0FH
12H
13H
14H
15H
16H
17H
18H
19H
1EH
1FH
Page0
Device Status Register (DSR) / Back-pressure Jam Limit Count (BJLC)
Current TX End Page Register (CTEPR) / VLAN_ID_0
Software Reset / Host Wake up (HWAKE)
Buffer Type Configure Register (BTCR)
Reserved / Big-Endian Register (BER)
Page1
Inter-frame Gap Segment 1 (IFGS1)
Inter-frame Gap Segment 2 (IFGS2)
MAC Configure Register (MCR)
Flow Control Register (FCR)
Command Register (CR)
Reserved / VLAN_ID_1
Max Frame Size [11:8]
MII/EEPROM Access
Inter-frame Gap (IFG)
Max Frame Size [7:0]
30
Data Port (DP)
AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION
Page2
Page3
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