M12L16161A-5T ESMT [Elite Semiconductor Memory Technology Inc.], M12L16161A-5T Datasheet - Page 2

• Manufacturer Part Number: M12L16161A-5T
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Elite Semiconductor Memory Technology Inc.
CLK
CKE
A0 ~ A10/AP Address
BA
L(U)DQM
DQ
V
CS
CAS
RAS
WE
DD
0 ~ 15
/V
Pin
SS
System Clock
Chip Select
Clock Enable
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
ADD
CLK
Name
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z,
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
CAS low.
CS
LWE
Timing Register
RAS
LCAS
CAS
P.2
Latency & Burst Length
Programming Register
Data Input Register
512K x 16
512K x 16
Column Decoder
WE
t
SHZ
L(U)DQM
LWCBR
Input Function
after the clock and masks the output.
Publication Date : Jan. 2000
LDQM
M12L16161A
LWE
LDQM
DQi
Revision : 1.3u