MN838898 PANASONIC [Panasonic Semiconductor], MN838898 Datasheet

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MN838898

Manufacturer Part Number
MN838898
Description
CMOS LSI source driver for color TFT LCD panels
Manufacturer
PANASONIC [Panasonic Semiconductor]
Datasheet
MN838898
Publication date: August 2002
Color TFT LCD Driver
1. Type
3. Features
2. Overview
(10) Automatic internal clock stop after fixed number of data inputs
(11) Choice of shift register shift direction: right or left
(12) Gray scale data inversion available every clock cycle
(13) Low voltage operation: 2.5 V (typ.) for logic circuits; 3.5 V (typ.)
(14) Maximum operating clock frequency: 15 MHz
(15) Power save function for cutting off current to outputs, fixing them
CMOS LSI source driver for color TFT LCD panels
This LSI converts the digital display data from a personal computer, portable
device, or other source into analog signals for driving a color TFT LCD panel.
(1) Power saving driver
(2) Built in DA converter accepting 6-bit digital input (for 262,144 colors)
(3) Choice of 360 and 324 drive outputs
(4) Input data bus at pixel level
(5) Choice of output data format: gray scale or binary
(6) Eleven reference voltage inputs for producing 10 segment gamma
(7) Set output voltage inflection points at data values 00, 01, 07, 0F, 17, 1F,
(8) Prechargeless drive circuits
(9) Support for serial cascade connections
adjustment graph.
27, 2F, 37, 3E, and 3F.
for analog circuits
at high impedance
SDF00030AEM
1

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MN838898 Summary of contents

Page 1

... Color TFT LCD Driver MN838898 1. Type CMOS LSI source driver for color TFT LCD panels 2. Overview This LSI converts the digital display data from a personal computer, portable device, or other source into analog signals for driving a color TFT LCD panel. 3. Features (1) Power saving driver ...

Page 2

... MN838898 4. Internal Block Diagram YX1 AV DD2 AV SS2 AV DD1 AV SS1 REF MODE2 LD INV 6 DX0 Latch 6 DY0 DZ0 to 5 STHR STHL NTEST YY1 YZ1 Output circuits DA converter 6 6 Two line latches, 360/324 × 6 bits Shift register, 120/108 bits ...

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... MN838898 ) 5. Pin Descriptions I/O Pin Name Direction DX0 to 5, DY0 to 5, Input DZ0 to 5 YX1 to 120, Output YY1 to 120, YZ1 to 120 STH R, STHL I/O RL Input FY Input LD Input INV Input Input MODE1 MODE2 Input PS Input NTEST Input VREF Input Input ...

Page 4

... MN838898 6. Description of Operation 6.1 Functional Description The MODE2 pin offers a choice of 6-bit gray scale data or 1-bit binary data. The MODE1 pin specifies the number of outputs. The following Table summarizes the effects of MODE1 and MODE2, and RL input levels on I/O. Input pins MODE2 RL MODE1 DX0 - 5 ...

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... MN838898  6.2 Relationships Between Data Input and Output Pins (1) Gray scale data input (MODE2 = Low) The following summarizes the relationships between data input and output pins for gray scale data input (MODE2 = Low). So, binary data input is naturally ignored during gray scale data input. ...

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... MN838898 6.3 Power Save Function This signal can be switched anywhere except the latch signal, rising edges in the FY signal.   YX01 to 120, YY01 to 120, YZ01 to 120 6.4 Blanking Interval The following timing chart summarizes the relationships between the load data (LD) and start pulse (STHR and STHL) inputs and the blanking interval. ...

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... MN838898 6.6 Switching Input Formats   The following timing chart summarizes the relationships between changes in input format and the subsequent changes in output. FY Start pulse inputs STHR (RL = High) STHL (RL = Low) MODE2 LD Valid input data YX1 to 120, YY1 to 120, YZ1 to 120   The LSI drives the output pins at high-impedance for one FY cycle when changing output formats ...

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... MN838898  6.7 Cascade Connection ( High Driver A starts latching data one FY cycle after receiving a start pulse (STHR). It asserts the carry signal (STHL) one FY cycle before latching the last data and then stopping. MODE1 = High (360 outputs): 119 FY cycles MODE1 = Low (324 outputs): 107 FY cycles Cascade Connection Driver B starts latching data one FY cycle after receiving the carry signal (STHL) from driver A ...

Page 9

... MN838898 6.8 Relationship between Input Data and Output Voltage 6.8.1 Built-In Gamma Adjustment Resistors The output voltage depends on the input data and thirteen gamma adjustment voltages ( 10, L). See graph and conversion table on the next two pages. REF x V REF 0 V REF 1 ...

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... MN838898 6.8.2 Relationship between Input Data and Output Voltage The following Figure gives the gamma adjustment curve for INV = Low REF 0 V REF 1 V REF 2 V REF 3 V REF 4 V REF 5 V REF 6 V REF 7 V REF 8 V REF 9 V REF 10 ...

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... MN838898 6.8.3 Relationship between Reference Voltages and Output Voltages The following Table gives the formulas for converting input data for INV = Low. Table 6.8 Relationship between Reference Voltages and Output Voltages (AV Input Formula for calculating output voltage data 00h V REF0 01h V REF2 02h ...

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... MN838898 7. Product Standards A. Absolute Maximum Ratings Digital power supply A1 voltage Analog power supply A2 voltage A3 Digital input voltage A4 Analog input voltage A5 Digital output voltage A6 Analog output voltage Operating storage A7 temperature Operating ambient A8 temperature A9 Storage temperature Note: The above absolute maximum ratings represent limits for avoiding damage to the product. They do not guarantee operation. · ...

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... MN838898 B. Operating Conditions Item Digital power supply B1 voltage Analog power supply B2 voltage Gamma adjustment B3 reference voltages B4 Operating frequency B5 Drive load capacity Digital signal input B6 capacity Notes (1) Use only direct connections to power supply pins sharing the same symbol (AV (2) Use only direct connections to ground pins sharing the same symbol (AV (3) Apply voltages in the following order: DV Remove them in the reverse order ...

Page 14

... MN838898 C. Electrical Characteristics ( 1) DC Characteristics Item Analog operation C1 power supply current (1) Analog operation C2 power supply current (2) Analog standby power C3 supply current Digital operation C4 power supply voltage Digital standby C5 power supply current ( 4) Typical conditions FY frequency of 15 MHz, raster period of 15 kHz, data pattern alternating between 00 and 3F every ...

Page 15

... MN838898 Item 1) Input pins (RL, LD, DX0 to 5, DY0 High level input C7 Low level input C8 Input leak current 2) I/O pins (STHR, STHL) High level input C9 C10 Low level input High level output C11 Low level output C12 Input leak current C13 ...

Page 16

... MN838898 Item (3) Gamma adjustment resistances C17 Resistance (4) Analog output pins (YX1 to 120, YY1 to 120, YZ1 to 120) High level output current C18 (gray scale output) Low level output current C19 (gray scale output) Average output C20 voltage deviation C21 Output voltage range ...

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... MN838898 (2) AC Characteristics Item C24 FY period C25 FY High level pulse width C26 FY Low level pulse width C27 Data/INV setup time C28 Data/INV hold time C29 Start pulse setup time C30 Start pulse hold time C31 Start pulse Low level pulse width ...

Page 18

... MN838898 AC Characteristics Timing Chart 1 DX0 to 5 DY0 to 5 DZ0 to 5 INV1 Input STHR (RL = High), STHL (RL = Low) Output STHL (RL = High) STHR (RL = Low Input STHR(RL = High), STHL(RL = Low) DX0 to 5, DY0 to 5, DZ0 to 5, INV1 MODE2 wcH st2 ...

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... MN838898 AC Characteristics Timing Chart st4 hd4 LD YX1 to 120, YY1 to 120, YZ1 to 120 FY LD DX0 to 5 DY0 to 5 DZ0 to 5 VALID INV1 FY t st6 PS YX1 to 120, YY1 to 120, YZ1 to 120 ng2 t st1 VALID VALID VALID t hd6 t d4 High-impedance output ...

Page 20

... No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. ...

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