LPC2138FBD64/01-S NXP Semiconductors, LPC2138FBD64/01-S Datasheet - Page 12

• Manufacturer Part Number: LPC2138FBD64/01-S
• Description: Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
LPC2131_32_34_36_38_4
Product data sheet
Symbol
P1.24/
TRACECLK
P1.25/EXTIN0
P1.26/RTCK
P1.27/TDO
P1.28/TDI
P1.29/TCK
P1.30/TMS
P1.31/TRST
RESET
XTAL1
XTAL2
RTCX1
RTCX2
V
V
V
V
VREF
VBAT
SS
SSA
DD
DDA
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
Open drain 5 V tolerant digital I/O I
functionality.
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value ranges from 60 k to 300 k .
5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
Pad provides special analog functionality.
Pin description
Pin
32
28
24
64
60
56
52
20
57
62
61
3
5
6, 18, 25, 42,
50
59
23, 43, 51
7
63
49
[8]
[8]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[7]
[8]
[8]
…continued
Type
O
I
I/O
O
I
I
I
I
I
I
O
I
O
I
I
I
I
I
I
2
C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
Description
TRACECLK — Trace Clock. Standard I/O port with internal pull-up.
EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.
RTCK — Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bidirectional pin with internal pull-up. LOW on RTCK while RESET is LOW
enables pins P1.31:26 to operate as Debug port after reset.
TDO — Test Data out for JTAG interface.
TDI — Test Data in for JTAG interface.
TCK — Test Clock for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Ground: 0 V reference.
Analog ground: 0 V reference. This should nominally be the same voltage
as V
3.3 V power supply: This is the power supply voltage for the core and I/O
ports.
Analog 3.3 V power supply: This should be nominally the same voltage as
V
to power the on-chip PLL.
ADC reference: This should be nominally the same voltage as V
should be isolated to minimize noise and error. Level on this pin is used as a
reference for A/D and D/A convertor(s).
RTC power supply: 3.3 V on this pin supplies the power to the RTC.
DD
Rev. 04 — 16 October 2007
SS
but should be isolated to minimize noise and error. This voltage is used
, but should be isolated to minimize noise and error.
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2007. All rights reserved.
DD
but
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