LPC2138FBD64/01-S NXP Semiconductors, LPC2138FBD64/01-S Datasheet - Page 19

• Manufacturer Part Number: LPC2138FBD64/01-S
• Description: Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2131_32_34_36_38_4
Product data sheet
6.12.1 Features
6.13.1 Features
6.14.1 Features
6.13 SSP serial I/O controller
6.14 General purpose timers/external event counters
The LPC2131/32/34/36/38 each contain one Serial Synchronous Port controller (SSP).
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. However, only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. Often only one of these data flows carries
meaningful data.
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock, and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
At any given time only one of peripheral’s capture inputs can be selected as an external
event signal source, i.e., timer’s clock. The rate of external events that can be successfully
counted is limited to PCLK/2. In this configuration, unused capture lines can be selected
as regular timer capture inputs.
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Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four bits to 16 bits per frame.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
External Event Counter or timer operation.
Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
Rev. 04 — 16 October 2007
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2007. All rights reserved.
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