STMPE1801BJR STMicroelectronics, STMPE1801BJR Datasheet - Page 31

• Manufacturer Part Number: STMPE1801BJR
• Description: Touch Screen Converters & Controllers Xpander Logic 18-Bit 18 GPIO 1.65 to 3.6V
• Manufacturer: STMicroelectronics

Specifications of STMPE1801BJR

• Rohs: yes
• Input Type: 1 Keypad
• Data Rate: 400 kbps
• Resolution: 18 bit
• Interface Type: I2C
• Supply Voltage: 1.65 V to 3.6 V
• Supply Current: 28 uA
• Operating Temperature: - 40 C to + 85 C
• Package / Case: CSP-25
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 1.65 V

STMPE1801
9.3
Programming sequence
To configure and initialize the interrupt controller to allow interruption to host, observe the
following steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Once the interrupt is cleared, the INT pin is also de-asserted if the interrupt type is level
11. When the interrupt function is no longer required, the IC0 bit in INT_CTRL may be set
Set the INT_EN_MASK and INT_EN_GPIO_MASK registers to the desired values to
enable the interrupt sources that are to be expected to receive from.
Configure the output interrupt type and polarity and enable the global interrupt mask by
writing to the INT_CTRL.
Wait for interrupt.
Upon receiving an interrupt, the corresponding INT bit is asserted.
The host comes to read the INT_STA register through the I
INT_STA bits indicates that the corresponding interrupt source is triggered.
If the IS3 bit in INT_STA register is set, the interrupt is coming from the GPIO controller.
Then, a subsequent read is performed on the INT_STA_GPIO register to obtain the
interrupt status of all 18 GPIOs to locate the GPIO that triggers the interrupt. This is a
‘Hot Key’ feature.
After obtaining the interrupt source that triggers the interrupt, the host performs the
necessary processing and operations related to the interrupt source.
All IS[x] bits in INT_STA register and ISG[x] bits in INT_STA_GPIO register which are
set to ‘1’ prior to the read event are cleared to ‘0’ automatically once the reading of the
registers are completed.
Any interrupt inputs received between reading and auto clearing of the registers are
kept in a shadow register and updated into the INT_STA and INT_STA_GPIO registers
once the auto clearing is completed.
interrupt. An edge interrupt only asserts a pulse width of 200 µs.
to ‘0’ to disable the global interrupt mask bit.
Doc ID 17884 Rev 3
2
C interface. A ‘1’ in the
Interrupt system
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