MAX1034BEUG+ Maxim Integrated, MAX1034BEUG+ Datasheet - Page 5

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MAX1034BEUG+

Manufacturer Part Number
MAX1034BEUG+
Description
Analog to Digital Converters - ADC 8-/4-Channel, Multirange Inputs,
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1034BEUG+

Rohs
yes
Number Of Channels
8/4
Architecture
SAR
Conversion Rate
115 kSPs
Resolution
14 bit
Input Type
Single-Ended/Differential
Snr
84.5 dB
Interface Type
3-Wire, QSPI, SPI
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-24
Maximum Power Dissipation
1111.1 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
4.136 V
ELECTRICAL CHARACTERISTICS (continued)
(V
external clock mode, V
C
Preamplifier Supply Voltage
Digital I/O Supply Voltage
AVDD1 Supply Current
DVDD Supply Current
AVDD2 Supply Current
DVDDO Supply Current
Total Supply Current
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS (Figures 15 and 16)
SCLK Period
SCLK High Pulse Width (Note 6)
SCLK Low Pulse Width (Note 6)
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Fall to SCLK Rise Setup
CS High Minimum Pulse Width
SCLK Fall to CS Rise Hold
SSTRB Rise to CS Fall Setup
DOUT Rise/Fall Time
SSTRB Rise/Fall Time
DOUT
AVDD1
= 50pF, C
= V
PARAMETER
AVDD2
SSTRB
= V
_______________________________________________________________________________________
REF
DVDD
= 50pF, T
= 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±V
8-/4-Channel, ±V
= V
DVDDO
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
SYMBOL
= 5V, V
V
V
I
I
I
I
DVDDO
t
AVDD1
AVDD2
PSRR
DVDDO
AVDD2
DVDD
CSPW
t
t
t
t
t
CSH
t
t
t
t
t
CSS
DO
CH
DH
CP
CL
DS
DV
TR
AGND1
External clock mode,
external acquisition
mode, or internal
clock mode
External clock mode, external acquisition
mode, or internal clock mode
External clock mode, external acquisition
mode, or internal clock mode
External clock mode, external acquisition
mode, or internal clock mode
Partial power-down mode
Full power-down mode
All analog input ranges
External clock mode
External acquisition mode
Internal clock mode
External clock mode
External acquisition mode
Internal clock mode
External clock mode
External acquisition mode
Internal clock mode
(Note 4)
C
C
L
L
= V
= 50pF
= 50pF
DGND
= V
DGNDO
CONDITIONS
REF
= V
Internal reference
External reference
AGND2
Serial 14-Bit ADCs
Multirange Inputs,
= V
AGND3
= 0V, f
A
0.272
0.288
4.75
2.70
MIN
109
109
= +25°C.)
0.1
92
40
92
40
40
40
40
40
CLK
0
0
= 3.5MHz (50% duty cycle),
±0.125
TYP
2.5
0.9
0.2
1.3
12
10
10
3
2
MAX
5.25
5.25
3.5
20
62
62
40
40
40
3
2
1
UNITS
LSB
mA
mA
mA
mA
mA
µA
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
REF
5
),

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