SSTVF16859BS,157 NXP Semiconductors, SSTVF16859BS,157 Datasheet - Page 2
![IC BUFFER DDR 13BIT 56-HVQFN](/photos/6/90/69032/568-56-hvqfn_sot684-1_sml.jpg)
SSTVF16859BS,157
Manufacturer Part Number
SSTVF16859BS,157
Description
IC BUFFER DDR 13BIT 56-HVQFN
Manufacturer
NXP Semiconductors
Series
SSTr
Datasheet
1.SSTVF16859BS118.pdf
(23 pages)
Specifications of SSTVF16859BS,157
Logic Type
Registered Buffer for DDR
Supply Voltage
2.3 V ~ 2.7 V
Number Of Bits
13, 26
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276956157
SSTVF16859BS
SSTVF16859BS
SSTVF16859BS
SSTVF16859BS
Philips Semiconductors
2. Features
3. Quick reference data
4. Ordering information
9397 750 15157
Product data sheet
Table 1:
GND = 0 V; T
[1]
Table 2:
T
Symbol
t
C
Type number
SSTVF16859BS
SSTVF16859DGG TSSOP64 plastic thin shrink small outline package; 64 leads;
SSTVF16859EC
PHL
amb
i
Stub-series terminated logic for 2.5 V V
Designed for PC1600-PC2700 (at 2.5 V) and PC3200 (at 2.6 V) applications
Pin and function compatible with JEDEC standard SSTV16859
Supports SSTL_2 signal inputs as per JESD 8-9
Flow-through architecture optimizes printed-circuit board layout
ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds
2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA
Supports efficient low power standby operation
Full DDR solution when used with PCKVF857
Available in TSSOP64, LFBGA96 and HVQFN56 packages
/t
C
P
f
C
f
V
i
o
= 0 C to +70 C
PLH
D
DD
PD
= input frequency in MHz;
L
(C
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
PD
V
Quick reference data
Ordering information
DD
Parameter
propagation delay,
CK/CK to Qn
input capacitance
amb
V
2
DD
= 25 C; t
f
2
o
) = sum of the outputs.
Package
Name
HVQFN56 plastic thermal enhanced very thin quad flat package;
LFBGA96 plastic low profile fine-pitch ball grid array package;
f
i
+
Rev. 02 — 19 July 2005
(C
r
= t
L
f
V
Description
no leads; 56 terminals; body 8
body width 6.1 mm
96 balls; body 13.5
DD
2.5 ns
2
f
o
) where:
Conditions
C
V
V
DD
DD
13-bit 1 : 2 SSTL_2 registered buffer for DDR
L
DD
= 30 pF;
= 2.5 V
= 2.5 V
(SSTL_2)
5.5
D
in W).
1.05 mm
[1]
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Min
-
-
8
SSTVF16859
0.85 mm
Typ
1.7
2.8
Max
-
-
Version
SOT684-1
SOT646-1
SOT536-1
Unit
ns
pF
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