IDT74SSTU32865BKG IDT, Integrated Device Technology Inc, IDT74SSTU32865BKG Datasheet - Page 6

• Manufacturer Part Number: IDT74SSTU32865BKG
• Description: IC BUFFER 28BIT 1:2 REG 160TFBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTU32865BKG

• Logic Type: 1:2 Registered Buffer with Parity
• Number Of Bits: 28
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-TFBGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 270(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Supply Voltage: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74SSTU32865BKG

PARITY AND STANDBY FUNCTION TABLE
NOTES:
1. H = HIGH Voltage Level
2. PARIN arrives one clock cycle after the data to which it applies
3. This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles, or until
RESET is driven LOW.
4. Output level before the indicated steady-state conditions were established.
IDT74SSTU32865
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
RESET
H
H
H
H
H
H
H
H
H
H
L
X or Floating
DCS0
H
H
H
H
H
L
L
L
L
X
X or Floating
DCS1
H
H
H
H
H
X
L
L
L
L
X or Floating
Inputs
L or H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X or Floating
L or H
CLK
↓
↓
↓
↓
↓
↓
↓
↓
↓
6
(1)
Σ Σ Σ Σ Σ of Inputs = H (D0 - D21)
X or Floating
Even
Even
Even
Even
Odd
Odd
Odd
Odd
X
X
COMMERCIAL TEMPERATURE RANGE
X or Floating
PARIN
H
H
H
H
L
L
L
L
X
X
(2)
PYTERR
PYTERR
PYTERR
Output
H
H
H
H
H
L
L
L
L
0
0
(3)
(4)
(4)