IDT74SSTUBF32865ABK IDT, Integrated Device Technology Inc, IDT74SSTUBF32865ABK Datasheet - Page 10

• Manufacturer Part Number: IDT74SSTUBF32865ABK
• Description: IC BUFFER 28BIT 1:2 REG 160-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTUBF32865ABK

• Number Of Bits: 28
• Logic Type: 1:2 Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BGA
• Logic Family: SSTU
• Logical Function: Reg Bfr W/ParityTst
• Number Of Elements: 1
• Number Of Inputs: 28
• Number Of Outputs: 56
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 160
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 74SSTUBF32865ABK

28-BIT 1:2 REGISTERED BUFFER WITH PARITY
IDT74SSTUBF32865A
28-BIT 1:2 REGISTERED BUFFER WITH PARITY
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol Parameter
t
PDMSS
Symbol
t
t
f
PDM
1
minimum time of t
2
time of t
3
PDQ 2
t
t
1
2
f
MAX
t
t
t
PHL
PLH
CLOCK
INACT
LH
HL
t
t
ACT
t
SU
t
W
H
1
V
V
t
Design target as per JEDEC specifications.
Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
SU
1
REF
REF
= 700ps for DCSx exiting Suspention Mode.
INACT
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK↑ / CLK↓ to Qn
Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn
Propagation Delay, simultaneous switching, CLK↑ / CLK↓ to Qn
LOW to HIGH Propagation Delay, CLK↑ / CLK↓ to PTYERR
HIGH to LOW Propagation Delay, CLK↑ / CLK↓ to PTYERR
HIGH to LOW Propagation Delay, RESET↓ to Qn↓
LOW to HIGH Propagation Delay, RESET↓ to PTYERR↑
, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
Parameter
Clock Frequency
Pulse Duration; CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup
(max) after RESET is taken LOW.
Time
Time
Hold
ACT
(max) after RESET is taken HIGH.
DCS0 before CLK↑ , CLK↓, DCS and CSGateEN
HIGH; DCS1 before CLK↑ , CLK↓, DCS0 and
CSGateEN HIGH
DCSn, DODT, DCKE, and Dn after CLK↑ , CLK↓
PARIN after CLK↑ , CLK↓
DCSn, DODT, DCKE, and Dn after CLK↑ , CLK↓
PARIN after CLK↑ , CLK↓
3
1
2
10
COMMERCIAL TEMPERATURE GRADE
V
V
Min.
Min.
DD
DD
410
0.6
0.5
0.5
0.4
0.4
1.1
0.4
1.2
1.0
1
= 1.8V ± 0.1V
= 1.8V ± 0.1V
IDT74SSTUBF32865A
Max.
Max.
410
1.5
0.8
1.6
10
15
3
3
3
3
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7092/11