SSTUAF32869AHLF IDT, Integrated Device Technology Inc, SSTUAF32869AHLF Datasheet

SSTUAF32869AHLF

Manufacturer Part Number

SSTUAF32869AHLF

Description

IC REGIST BUFF 25BIT DDR2 150BGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.SSTUAF32869AHLFT.pdf (20 pages)

Specifications of SSTUAF32869AHLF

Logic Type

1:2 Configurable Registered Buffer

Supply Voltage

1.7 V ~ 1.9 V

Number Of Bits

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

150-CABGA, CTBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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Company:

BOSTOCK HK LIMITED

Part Number:

SSTUAF32869AHLF

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

SSTUAF32869AHLFT

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description

The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with

parity, designed for 1.7 V to 1.9 V V

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8V CMOS drivers optimized to drive the

DDR2 DIMM load. They provide 50% more dynamic driver

strength than the standard SSTU32864 outputs.

The ICSSSTUAF32869A operates from a differential clock

(CLK and CLK). Data are registered at the crossing of CLK

going high, and CLK going low.

The device supports low-power standby operation. When

the reset input (RESET) is low, the differential input

receivers are disabled, and undriven (floating) data, clock

and reference voltage (V

addition, when RESET is low all registers are reset, and all

outputs except PTYERR are forced low. The LVCMOS

RESET input must always be held at a valid logic high or

low level.

To ensure defined outputs from the register before a stable

clock has been supplied, RESET must be held in the low

state during power up.

In the DDR2 RDIMM application, RESET is specified to be

completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed

between the two. When entering reset, the register will be

cleared and the outputs will be driven low quickly, relative to

the time to disable the differential input receivers. However,

when coming out of reset, the register will become active

quickly, relative to the time to enable the differential input

receivers. ICSSSTUAF32869A must ensure that the

outputs remain low as long as the data inputs are low, the

clock is stable during the time from the low-to-high

transition of RESET and the input receivers are fully

enabled. This will ensures that there are no glitches on the

output.

The device monitors both DCS and CSR inputs and will

gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity

Error) Parity outputs from changing states when both DCS

and CSR are high. If either DCS and CSR input is low, the

Qn, PPO and PTYERR outputs will function normally. The

RESET input has priority over the DCS and CSR controls

and will force the Qn and PPO outputs low and the

PTYERR high.

14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

REF

) inputs are allowed. In

operation.

The ICSSSTUAF32869A includes a parity checking

function. The ICSSSTUAF32869A accepts a parity bit from

the memory controller at its input pin PARIN one or two

cycles after the corresponding data input, compares it with

the data received on the D-inputs and indicates on its

opendrain PTYERR pin (active low) whether a parity error

has occurred. The number of cycles depends on the setting

of C1.

When used as a single device, the C1 input is tied low.

When used in pairs, the C1 inputs is tied low for the first

PTYERR signals are produced two clock cycles after the

corresponding data input. When used in pairs, the PTYERR

signals of the first register are left floating. The PPO outputs

of the first register are cascaded to the PARIN signas on the

second register (back). The PPO and PTYERR signals of

the second register are produced three clock cycles after

the corresponding data input. Parity implimentation and

device wiring for single and dual die is described in the

diagram below.

If an error occurs, and the PTYERR is driven low, it stays

low for two clock cycles or until RESET is driven low. The

DIMM-dependent signals (DCKE, DCS, CSR and DODT)

are not included in the parity check computations.

All registers used on an individual DIMM must be of the

same configuration, i.e single or dual die.

Features

•

Applications

•

14-bit 1:2 registered buffer with parity check functionality

Supports SSTL_18 JEDEC specification on data inputs

and outputs

50% more dynamic driver strength than standard

SSTU32864

Supports LVCMOS switching levels on C1 and RESET

inputs

Low voltage operation: V

Available in 150 BGA package

DDR2 Memory Modules

Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

Ideal for DDR2 400, 533, and 667

ICSSSTUAF32869A

= 1.7V to 1.9V

ICSSSTUAF32869A

DATASHEET

7095/14

Related parts for SSTUAF32869AHLF

SSTUAF32869AHLF Summary of contents

Page 1

CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description The ICSSSTUAF32869A is 14-bit 1:2 registered buffer with parity, designed for 1 1 All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs ...

Page 2

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity Implementation and Device Wiring PARIN, W4 PARIN NC, A8 Block Diagram V REF PARIN D1 (1) D14 DCS0 CSR DCKE DODT RESET CLK CLK NOTE: 1.This range does not include D1, D4, ...

Page 3

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Block Diagram RESET CLK CLK D14 V REF 2 PARIN C1, C2 NOTE: 1.PARIN is used to generate PPO and PTYERR. 14-BIT CONFIGURABLE REGISTERED ...

Page 4

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Pin Configuration QCKEA D Q2A E Q3A F QODTA G Q5A H Q6A J QCSA Q8A M Q9A N Q10A P Q11A ...

Page 5

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 150 Ball CTBGA Package Attributes Top Marking TOP ...

Page 6

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Function Table RESET DCS CSR ...

Page 7

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Terminal Functions Signal Terminal Group Name Ungated DCKE, DODT Inputs Chip Select D1...D14 Gated Inputs Chip Select DCS, CSR Inputs Q1A...Q14A Q1B...Q14B Re-Driven QCSnA, B Outputs QCKEnA, B QODTnA, B Parity Input PARIN ...

Page 8

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Parity and Standby Function Table RESET DCS CSR ...

Page 9

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...

Page 10

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Operating Characteristics, T The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET ...

Page 11

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter PTYERR Output V ERROL ...

Page 12

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time ACT 2 t Differential ...

Page 13

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range Parameter dV/dt_r dV/dt_f 1 dV/dt_∆ 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 14-BIT CONFIGURABLE REGISTERED BUFFER ...

Page 14

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET DCS CSR CLK CLK ( D14 ( Q14 (2) PARIN (2) PPO (2) PTYERR NOTES: 1.This range does not include D1, D4, and D7, and their ...

Page 15

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Register Timing RESET DCS CSR CLK CLK ( D14 ( Q14 (2) PARIN (2) PPO (not used) (2) PTYERR NOTES: 1.This range does not include D1, D4, and D7, ...

Page 16

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT CLK Out CLK Inputs CLK Test Point R 100 L = Test Point Simulation Load Circuit LVCMOS RESET Input t ...

Page 17

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...

Page 18

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Test Circuits and Waveforms (V DUT CLK CLK Output Partial Parity Out Voltage Waveform, Propagation Delay Time with Respect to CLK Input Cross Point Voltage ICR ...

Page 19

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Ordering Information ICSSSTUAF XX XXX Family Device Type 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 XX X Package Shipping Carrier T Tape and Reel HLF Low Profile, Fine Pitch, Ball Grid Array - Lead-Free ...

Page 20

ICSSSTUAF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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