LCMXO1200E-4TN144I Lattice, LCMXO1200E-4TN144I Datasheet - Page 10
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LCMXO1200E-4TN144I
Manufacturer Part Number
LCMXO1200E-4TN144I
Description
CPLD - Complex Programmable Logic Devices 1200 LUTs 113 IO 1.2 V -4 Spd I
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-5TN100C.pdf
(96 pages)
Specifications of LCMXO1200E-4TN144I
Rohs
yes
Memory Type
SRAM
Number Of Macrocells
600
Maximum Operating Frequency
550 MHz
Delay Time
4.4 ns
Number Of Programmable I/os
113
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
300
Supply Current
18 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO1200E-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock/Control Distribution Network
The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four
primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in
Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual
function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and
MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL out-
puts.
Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices
Routing
12
Clock
Pads
4
2-7
16:1
16:1
16:1
16:1
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
MachXO Family Data Sheet
Architecture