LCMXO1200E-4TN144I Lattice, LCMXO1200E-4TN144I Datasheet - Page 96
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO1200E-4TN144I
Manufacturer Part Number
LCMXO1200E-4TN144I
Description
CPLD - Complex Programmable Logic Devices 1200 LUTs 113 IO 1.2 V -4 Spd I
Manufacturer
Lattice
Datasheet
1.LCMXO1200C-5TN100C.pdf
(96 pages)
Specifications of LCMXO1200E-4TN144I
Rohs
yes
Memory Type
SRAM
Number Of Macrocells
600
Maximum Operating Frequency
550 MHz
Delay Time
4.4 ns
Number Of Programmable I/os
113
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
300
Supply Current
18 mA
Supply Voltage - Max
1.26 V
Supply Voltage - Min
1.14 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO1200E-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
November 2006
December 2006
November 2007
February 2007
August 2007
June 2009
July 2010
Date
Version
02.3
02.4
02.5
02.6
02.7
02.8
02.9
Ordering Information
Pinout Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Characteristics
Supplemental
Architecture
Architecture
Introduction
Information
Section
Corrections to MachXO “C” Sleep Mode Timing table - value for
t
(100ns) changed from min. to max.
Added Flash Download Time table.
EBR Asynchronous Reset section added.
Power Supply and NC table: Pin/Ball orientation footnotes added.
Updated EBR Asynchronous Reset section.
Updated sysIO Single-Ended DC Electrical Characteristics table.
Added JTAG Port Timing Waveforms diagram.
Added Thermal Management text section.
Updated title list.
Added 0.8-mm 256-pin caBGA package to MachXO Family Selection
Guide table.
Added Logic Signal Connections table for 0.8-mm 256-pin caBGA pack-
age.
Updated Part Number Description diagram and Ordering Part Number
tables with 0.8-mm 256-pin caBGA package information.
Updated sysCLOCK PLL Timing table.
WSLEEPN
7-3
(400ns) changed from max. to min. Value for t
Change Summary
MachXO Family Data Sheet
Revision History
WAWAKE