ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet - Page 20

• Manufacturer Part Number: ADC1213D080HN-C1
• Description: Analog to Digital Converters - ADC
• Manufacturer: IDT

Specifications of ADC1213D080HN-C1

• Rohs: yes

Integrated Device Technology
ADC1213D_SER 8
Product data sheet
11.3.3 Clock input divider
11.3.4 Duty cycle stabilizer
11.4.1 Serial output equivalent circuit
11.4 Digital outputs
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
The ADC1413D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12.
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
The output should be terminated when 100  (typical) is reached at the receiver side.
Bit DCS_EN
0
1
Fig 19. CML output connection to the receiver (DC-coupled)
Duty cycle stabilizer
+
Rev. 08 — 2 July 2012
12 mA to 26 mA
50 Ω
−
VDDD
CMLPA/CLMPB
CMLNA/CLMNB
AGND
Dual 12-bit ADC; serial JESD204A interface
Description
duty cycle stabilizer disable
duty cycle stabilizer enable
ADC1213D series
100 Ω
RECEIVER
005aaa082
© IDT 2012. All rights reserved.
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