ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet - Page 31

• Manufacturer Part Number: ADC1213D080HN-C1
• Description: Analog to Digital Converters - ADC
• Manufacturer: IDT

Specifications of ADC1213D080HN-C1

• Rohs: yes

Integrated Device Technology
Table 30.
Default values are highlighted.
Table 31.
Default values are highlighted.
Table 32.
Default values are highlighted.
ADC1213D_SER 8
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
7 to 2
1
0
Bit
7 to 3
2 to 0
Symbol
-
TRISTATE_CFG_PINS
SYNC_POL
SYNC_SINGLE_ENDED R/W
-
REV_SCR
REV_ENCODER
REV_SERIAL
Symbol
-
SWAP_LANE_1_2
SWAP_ADC_0_1
Symbol
-
SWING_SEL[2:0]
Ser_Control1 (address 0805h)
Ser_Control2 (address 0806h)
Ser_Analog_Ctrl (address 0808h)
Access
-
R/W
R/W
-
-
-
-
Access
-
R/W
R/W
Access
-
R/W
Value
0
1
0
1
0
1
1
0
1
0
1
0
1
Value
000000
0
1
0
1
Value
00000
011
Rev. 08 — 2 July 2012
Description
not used
pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
defines the sync signal polarity:
defines the input mode of the sync signal:
not used
LSBs are swapped with MSBs at the scrambler input:
LSBs are swapped with MSBs at the 8-bit/10-bit encoder input:
LSBs are swapped with MSBs at the lane input:
Description
not used
swaps the outputs of the JESD204A unit (output buffer A is
connected to Lane 1, output buffer B is connected to Lane 0):
swaps the inputs of the JESD204A unit (ADC A output is
connected to ADC input B, ADC B is connected to ADC input A):
Description
not used
defines the swing output for the lane pads
synchronization signal is active LOW
synchronization signal is active HIGH
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
disable
enable
disable
enable
disable
enable
disable
enable
disable
enable
Dual 12-bit ADC; serial JESD204A interface
ADC1213D series
© IDT 2012. All rights reserved.
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