ADC1213D080HN-C1 IDT, ADC1213D080HN-C1 Datasheet - Page 34

• Manufacturer Part Number: ADC1213D080HN-C1
• Description: Analog to Digital Converters - ADC
• Manufacturer: IDT

Specifications of ADC1213D080HN-C1

• Rohs: yes

Integrated Device Technology
Table 47.
Default values are highlighted.
Table 48.
Default values are highlighted.
Table 49.
Default values are highlighted.
Table 50.
Default values are highlighted.
ADC1213D_SER 8
Product data sheet
Bit
7 to 5
4 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7
6
5 to 4
3
2
1
Symbol
-
LID[4:0]
Symbol
FCHK[7:0]
Symbol
FCHK[7:0]
Symbol
-
SCR_IN_MODE
LANE_MODE[1:0]
-
LANE_POL
LANE_CLK_POS_EDGE R/W
Cfg_02_2_LID (address 082Dh)
Cfg01_13_FCHK (address 084Ch)
Cfg02_13_FCHK (address 084Dh)
Lane0_0_Ctrl (address 0870h)
Access
-
R/W
Access
R
Access
R
Access
-
R/W
R/W
-
R/W
Value
000
11100
Value
00000000 defines the checksum value for lane 0
Value
00000000 defines the checksum value for lane 1
Value
0
0 (reset)
1
00 (reset)
01
10
11
0
0
1
0
1
Rev. 08 — 2 July 2012
Description
not used
defines lane 1 identification number
Description
checksum corresponds to the sum of all the link configuration
parameters modulo 256 (as defined in JEDEC Standard
No.204A)
Description
checksum corresponds to the sum of all the link configuration
parameters module 256 (as defined in JEDEC Standard
No.204A)
Description
not used
defines the input type for scrambler and 8-bit/10-bit units:
defines output type of lane output unit:
not used
defines lane polarity:
defines lane clock polarity:
(normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE”
(Ser_PRBS_Ctrl register)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0  0)
toggle mode: lane output is toggling between 0  0 and 0  1
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
lane polarity is normal
lane polarity is inverted
lane clock provided to the serializer is active on positive
edge
lane clock provided to the serializer is active on negative edge
Dual 12-bit ADC; serial JESD204A interface
ADC1213D series
© IDT 2012. All rights reserved.
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